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? 2008 microchip technology inc. ds22059b-page 1 mcp414x/416x/424x/426x features single or dual resistor network options potentiometer or rheostat configuration options resistor network resolution - 7-bit: 128 resistors (129 steps) - 8-bit: 256 resistors (257 steps) r ab resistances options of: -5k ? -10k ? -50k ? - 100 k ? zero-scale to full-scale wiper operation low wiper resistance: 75 ? (typical) low tempco: - absolute (rheostat): 50 ppm typical (0c to 70c) - ratiometric (potentiometer): 15 ppm typical non-volatile memory - automatic recall of saved wiper setting - wiperlock? technology spi serial interface (10 mhz, modes 0,0 & 1,1) - high-speed read/writes to wiper registers - read/write to data eeprom registers - serially enabled eeprom write protect - sdi/sdo multiplexing (mcp41x1 only) resistor network terminal disconnect feature via: - shutdown pin (shdn ) - terminal control (tcon) register write protect feature: - hardware write protect (wp ) control pin - software write protect (wp) configuration bit brown-out reset protection (1.5v typical) serial interface inactive current (2.5 ua typical) high-voltage tolerant digital inputs: up to 12.5v supports split rail applications internal weak pull-up on all digital inputs wide operating voltage: - 2.7v to 5.5v - device characteristics specified - 1.8v to 5.5v - device operation wide bandwidth (-3db) operation: - 2 mhz (typical) for 5.0 k ? device extended temperature range (-40c to +125c) description the mcp41xx and mcp42xx devices offer a wide range of product offerings using an spi interface. wiperlock technology a llows application-specific calibration settings to be secured in the eeprom. package types (top view) 12 3 4 5 6 7 8 p0w p0b p0a v ss v dd mcp41x1 single potentiometer pdip, soic, msop cs sdi/sdo sck 12 3 4 5 6 7 8 p0b sdo p0w v dd mcp41x2 single rheostat pdip, soic, msop 12 3 4 11 12 13 14 shdn sdowp v dd mcp42x1 dual potentiometers pdip, soic, tssop 56 7 8 9 10 p0w p0b p0a p1a p1w p1b v ss cs sdi sck v ss cs sdi sck 4x4 qfn* 12 3 4 7 8 9 10 sdo v dd mcp42x2 dual rheostat msop, dfn 5 6 p0bp0w p1w p1b v ss cs sdi sck 3x3 dfn* sdi/sdo sck v ss p0bp0w 1 2 3 4 8 7 6 5 p0a cs ep 9 3x3 dfn* sdi sck v ss sdo p0b 1 2 3 4 8 7 6 5 p0w v dd cs ep 9 v dd 3x3 dfn* sdi sck v ss sdop0b 1 2 3 4 10 9 8 7 p0w cs ep 11 v dd 5 6 p1b p1w * includes exposed thermal pad (ep); see table 3-1 . 2 v ss v ss sck wp nc p1b p0b p1w p1a p0a p0w cs v dd sdoshdn sdi ep 16 1 15 14 13 34 12 11 10 9 5678 17 7/8-bit single/dual spi digital pot with non-volatile memory downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 2 ? 2008 microchip technology inc. device block diagram device features device # of pots wiper configuration control interface memory type wiperlock technology por wiper setting resistance (typical) # of steps v dd operating range (2) r ab options (k ) wiper - r w ( ) mcp4131 (3) 1 potentiometer (1) spi ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 129 1.8v to 5.5v mcp4132 (3) 1 rheostat spi ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 129 1.8v to 5.5v mcp4141 1 potentiometer (1) spi ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7v to 5.5v mcp4142 1 rheostat spi ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7v to 5.5v mcp4151 (3) 1 potentiometer (1) spi ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 257 1.8v to 5.5v mcp4152 (3) 1 rheostat spi ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 257 1.8v to 5.5v mcp4161 1 potentiometer (1) spi ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7v to 5.5v mcp4162 1 rheostat spi ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7v to 5.5v mcp4231 (3) 2 potentiometer (1) spi ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 129 1.8v to 5.5v mcp4232 (3) 2 rheostat spi ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 129 1.8v to 5.5v mcp4241 2 potentiometer (1) spi ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7v to 5.5v mcp4242 2 rheostat spi ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7v to 5.5v mcp4251 (3) 2 potentiometer (1) spi ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 257 1.8v to 5.5v mcp4252 (3) 2 rheostat spi ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 257 1.8v to 5.5v mcp4261 2 potentiometer (1) spi ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7v to 5.5v mcp4262 2 rheostat spi ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7v to 5.5v note 1: floating either terminal (a or b) allows the devi ce to be used as a rheostat (variable resistor). 2: analog characteristics only tested from 2.7v to 5.5v unless otherwise noted. 3: please check microchip web site for device release and availability power-up/ brown-out control v dd v ss spi serialinterface module & control logic (wiperlock? technology) resistor network 0 (pot 0) wiper 0 & tcon register resistor network 1 (pot 1) wiper 1 & tcon register cs sck sdi sdo wp shdn memory (16x9) wiper0 (v & nv) wiper1 (v & nv) tcon status data eeprom (10 x 9-bits) p0a p0w p0b p1a p1w p1b for dual resistor network devices only for dual potentiometer devices only downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 3 mcp414x/416x/424x/426x 1.0 electrical characteristics absolute maximum ratings ? voltage on v dd with respect to v ss ............... -0.6v to +7.0v voltage on cs , sck, sdi, sdi/sdo, wp , and shdn with respect to v ss ...................................... -0.6v to 12.5v voltage on all other pins (pxa, pxw, pxb, and sdo) with respect to v ss ............................ -0.3v to v dd + 0.3v input clamp current, i ik (v i < 0, v i > v dd , v i > v pp on hv pins) ......................20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ..................................................20 ma maximum output current sunk by any output pin ......................................................................................25 ma maximum output current sourced by any output pin ......................................................................................25 ma maximum current out of v ss pin .................................100 ma maximum current into v dd pin ....................................100 ma maximum current into p x a, p x w & p x b pins ............2.5 ma storage temperature ....................................-65c to +150c ambient temperature with power applied .....................................................................-40c to +125c total power dissipation ( note 1 ) ................................400 mw soldering temperature of leads (10 seconds) ............. +300c esd protection on all pins .................................. 4 kv (hbm), .......................................................................... 300v (mm) maximum junction temperature (t j ) ......................... +150c ? notice: stresses above those listed under maximum ratings may cause permanent dam age to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note 1: power dissipation is calculated as follows: p dis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v oi x i ol ) downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 4 ? 2008 microchip technology inc. ac/dc characteristics dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c t a +125c (extended) all parameters apply across the specif ied operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions supply voltage v dd 2.7 5.5 v 1.8 2.7 v serial interface only. cs , sdi, sdo, sck, wp , shdn pin voltage range v hv v ss 12.5v v v dd 4.5v the cs pin will be at one of three input levels (v il , v ih or v ihh ). ( note 6 ) v ss v dd + 8.0v vv dd < 4.5v v dd start voltage to ensure wiper reset v bor 1.65 v ram retention voltage (v ram ) < v bor v dd rise rate to ensure power-on reset v ddrr ( note 9 )v / m s delay after device exits the reset state (v dd > v bor ) t bord 1 02 0 s supply current (note 10) i dd 450 a serial interface active, v dd = 5.5v, cs = v il , sck @ 5 mhz, write all 0 s to volatile wiper 0 (address 0h) 1 ma ee write current, v dd = 5.5v, cs = v il , sck @ 5 mhz, write all 0 s to non-volatile wiper 0 (address 2h) 2.5 5 a serial interface inactive, cs = v ih , v dd = 5.5v 0.55 1 ma serial interface active, v dd = 5.5v, cs = v ihh , sck @ 5 mhz, decrement non-volatile wiper 0 (address 2h) note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and bs polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes signific antly over voltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp41x2 and mcp42x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 5 mcp414x/416x/424x/426x resistance ( 20%) r ab 4.0 5 6.0 k ? -502 devices (note 1) 8.0 10 12.0 k ? -103 devices (note 1) 40.0 50 60.0 k ? -503 devices (note 1) 80.0 100 120.0 k ? -104 devices (note 1) resolution n 257 taps 8-bit no missing codes 129 taps 7-bit no missing codes step resistance r s r ab / (256) ? 8-bit note 6 r ab / (128) ? 7-bit note 6 nominal resistance match |r ab0 - r ab1 | / r ab 0.2 1.25 % mcp42x1 devices only |r bw0 - r bw1 | / r bw 0 . 2 51 . 5 % mcp42x2 devices only, code = full-scale wiper resistance ( note 3, note 4) r w 75 160 ? v dd = 5.5 v, i w = 2.0 ma, code = 00h 75 300 ? v dd = 2.7 v, i w = 2.0 ma, code = 00h nominal resistance te m p c o r ab / t 50 ppm/c t a = -20c to +70c 100 ppm/c t a = -40c to +85c 150 ppm/c t a = -40c to +125c ratiometeric te m p c o v wb / t 15 ppm/c code = midscale (80h or 40h) resistor terminal input voltage range (terminals a, b and w) v a, v w, v b vss v dd v note 5, note 6 maximum current through a, w or b i w 2 . 5m a note 6 , worst case current through wiper when wiper is either full-scale or zero scale. leakage current into a, w or b i wl 1 0 0n a mcp4xx1 pxa = pxw = pxb = v ss 1 0 0n a mcp4xx2 pxb = pxw = v ss ac/dc characteristi cs (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c t a +125c (extended) all parameters apply across the specif ied operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and bs polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes signific antly over voltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp41x2 and mcp42x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 6 ? 2008 microchip technology inc. full-scale error ( mcp4xx1 only) (8-bit code = 100h, 7-bit code = 80h) v wfse -6.0 -0.1 lsb 5 k ? 8-bit 3.0v v dd 5.5v -4.0 -0.1 lsb 7-bit 3.0v v dd 5.5v -3.5 -0.1 lsb 10 k ? 8-bit 3.0v v dd 5.5v -2.0 -0.1 lsb 7-bit 3.0v v dd 5.5v -0.8 -0.1 lsb 50 k ? 8-bit 3.0v v dd 5.5v -0.5 -0.1 lsb 7-bit 3.0v v dd 5.5v -0.5 -0.1 lsb 100 k ? 8-bit 3.0v v dd 5.5v -0.5 -0.1 lsb 7-bit 3.0v v dd 5.5v zero-scale error ( mcp4xx1 only) (8-bit code = 00h, 7-bit code = 00h) v wzse + 0 . 1+ 6 . 0l s b5 k ? 8-bit 3.0v v dd 5.5v +0.1 +3.0 lsb 7-bit 3.0v v dd 5.5v +0.1 +3.5 lsb 10 k ? 8-bit 3.0v v dd 5.5v +0.1 +2.0 lsb 7-bit 3.0v v dd 5.5v +0.1 +0.8 lsb 50 k ? 8-bit 3.0v v dd 5.5v +0.1 +0.5 lsb 7-bit 3.0v v dd 5.5v +0.1 +0.5 lsb 100 k ? 8-bit 3.0v v dd 5.5v +0.1 +0.5 lsb 7-bit 3.0v v dd 5.5v potentiometer integral non-linearity inl -1 0.5 +1 lsb 8-bit 3.0v v dd 5.5v mcp4xx1 devices only (note 2) -0.5 0.25 +0.5 lsb 7-bit potentiometer differential non-linearity dnl -0.5 0.25 +0.5 lsb 8-bit 3.0v v dd 5.5v mcp4xx1 devices only (note 2) -0.25 0.125 +0.25 lsb 7-bit bandwidth -3 db (see figure 2-58 , load = 30 pf) bw 2 mhz 5 k ? 8-bit code = 80h 2 mhz 7-bit code = 40h 1m h z 1 0 k ? 8-bit code = 80h 1 mhz 7-bit code = 40h 2 0 0k h z5 0 k ? 8-bit code = 80h 200 khz 7-bit code = 40h 1 0 0k h z1 0 0 k ? 8-bit code = 80h 100 khz 7-bit code = 40h ac/dc characteristi cs (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c t a +125c (extended) all parameters apply across the specif ied operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and bs polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes signific antly over voltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp41x2 and mcp42x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 7 mcp414x/416x/424x/426x rheostat integral non-linearity mcp41x1 ( note 4, note 8 ) mcp4xx2 devices only (note 4) r-inl -1.5 0.5 +1.5 lsb 5 k ? 8-bit 5.5v, i w = 900 a -8.25 +4.5 +8.25 lsb 3.0v, i w = 480 a ( note 7 ) -1.125 0.5 +1.125 lsb 7-bit 5.5v, i w = 900 a -6.0 +4.5 +6.0 lsb 3.0v, i w = 480 a ( note 7 ) -1.5 0.5 +1.5 lsb 10 k ? 8-bit 5.5v, i w = 450 a -5.5 +2.5 +5.5 lsb 3.0v, i w = 240 a ( note 7 ) -1.125 0.5 +1.125 lsb 7-bit 5.5v, i w = 450 a -4.0 +2.5 +4.0 lsb 3.0v, i w = 240 a ( note 7 ) -1.5 0.5 +1.5 lsb 50 k ? 8-bit 5.5v, i w = 90 a -2.0 +1 +2.0 lsb 3.0v, i w = 48 a ( note 7 ) -1.125 0.5 +1.125 lsb 7-bit 5.5v, i w = 90 a -1.5 +1 +1.5 lsb 3.0v, i w = 48 a ( note 7 ) -1.0 0.5 +1.0 lsb 100 k ? 8-bit 5.5v, i w = 45 a -1.5 +0.25 +1.5 lsb 3.0v, i w = 24 a ( note 7 ) -0.8 0.5 +0.8 lsb 7-bit 5.5v, i w = 45 a -1.125 +0.25 +1.125 lsb 3.0v, i w = 24 a ( note 7 ) ac/dc characteristi cs (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c t a +125c (extended) all parameters apply across the specif ied operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and bs polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes signific antly over voltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp41x2 and mcp42x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 8 ? 2008 microchip technology inc. rheostat differential non-linearity mcp41x1 ( note 4, note 8 ) mcp4xx2 devices only (note 4) r-dnl -0.5 0.25 +0.5 lsb 5 k ? 8-bit 5.5v, i w = 900 a -1.0 +0.5 +1.0 lsb 3.0v ( note 7 ) -0.375 0.25 +0.375 lsb 7-bit 5.5v, i w = 900 a -0.75 +0.5 +0.75 lsb 3.0v ( note 7 ) -0.5 0.25 +0.5 lsb 10 k ? 8-bit 5.5v, i w = 450 a -1.0 +0.25 +1.0 lsb 3.0v ( note 7 ) -0.375 0.25 +0.375 lsb 7-bit 5.5v, i w = 450 a -0.75 +0.5 +0.75 lsb 3.0v ( note 7 ) -0.5 0.25 +0.5 lsb 50 k ? 8-bit 5.5v, i w = 90 a -0.5 0.25 +0.5 lsb 3.0v ( note 7 ) -0.375 0.25 +0.375 lsb 7-bit 5.5v, i w = 90 a -0.375 0.25 +0.375 lsb 3.0v ( note 7 ) -0.5 0.25 +0.5 lsb 100 k ? 8-bit 5.5v, i w = 45 a -0.5 0.25 +0.5 lsb 3.0v ( note 7 ) -0.375 0.25 +0.375 lsb 7-bit 5.5v, i w = 45 a -0.375 0.25 +0.375 lsb 3.0v ( note 7 ) capacitance (p a )c aw 75 pf f =1 mhz, code = full-scale capacitance (p w )c w 120 pf f =1 mhz, code = full-scale capacitance (p b )c bw 75 pf f =1 mhz, code = full-scale ac/dc characteristi cs (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c t a +125c (extended) all parameters apply across the specif ied operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and bs polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes signific antly over voltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp41x2 and mcp42x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 9 mcp414x/416x/424x/426x digital inputs/outputs (cs , sdi, sdo, sck, wp , shdn ) schmitt trigger high input threshold v ih 0.45 v dd v2 . 7 v v dd 5.5v (allows 2.7v digital v dd with 5v analog v dd ) 0.5 v dd v1 . 8 v v dd 2.7v schmitt trigger low input threshold v il 0.2v dd v hysteresis of schmitt trigger inputs v hys 0 . 1 v dd v high voltage input entry voltage v ihh 8.5 12.5 (6) v threshold for wiperlock? technology high voltage input exit voltage v ihh v dd + 0.8v (6) v high voltage limit v max 1 2 . 5 (6) v pin can tolerate v max or less. output low voltage (sdo) v ol v ss 0 . 3 v dd vi ol = 5 ma, v dd = 5.5v v ss 0 . 3 v dd vi ol = 1 ma, v dd = 1.8v output high voltage (sdo) v oh 0.7v dd v dd vi oh = -2.5 ma, v dd = 5.5v 0.7v dd v dd vi ol = -1 ma, v dd = 1.8v weak pull-up / pull-down current i pu 1.75 ma internal v dd pull-up, v ihh pull-down, v dd = 5.5v, v cs = 12.5v 1 7 0 ac s pin, v dd = 5.5v, v cs = 3v cs pull-up / pull-down resistance r cs 1 6k ? v dd = 5.5v, v cs = 3v input leakage current i il -1 1 a v in = v dd and v in = v ss pin capacitance c in , c out 1 0p ff c = 20 mhz ac/dc characteristi cs (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c t a +125c (extended) all parameters apply across the specif ied operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and bs polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes signific antly over voltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp41x2 and mcp42x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 10 ? 2008 microchip technology inc. ram (wiper) value value range n 0h 1ffh hex 8-bit device 0h 1ffh hex 7-bit device eeprom endurance e ndurance 1m cycles eeprom range n 0h 1ffh hex initial factory setting n 80h hex 8-bit wiperlock technology = off 40h hex 7-bit wiperlock technology = off eeprom pro- gramming write cycle time t wc 51 0m s power requirements power supply sensitivity ( mcp41x2 and mcp42x2 only) pss 0.0015 0.0035 %/% 8-bit v dd = 2.7v to 5.5v, v a = 2.7v, code = 80h 0.0015 0.0035 %/% 7-bit v dd = 2.7v to 5.5v, v a = 2.7v, code = 40h ac/dc characteristi cs (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c t a +125c (extended) all parameters apply across the specif ied operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and bs polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes signific antly over voltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp41x2 and mcp42x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 11 mcp414x/416x/424x/426x 1.1 spi mode timing waveforms and requirements figure 1-1: spi timing waveform (mode = 11). table 1-1: spi requirements (mode = 11 ) # characteristic symbol min max units conditions sck input frequency f sck 1 0m h zv dd = 2.7v to 5.5v 1m h z v dd = 1.8v to 2.7v 70 cs active (v il or v ihh ) to sck input tcsa2sch 60 ns 71 sck input high time tsch 45 ns v dd = 2.7v to 5.5v 500 ns v dd = 1.8v to 2.7v 72 sck input low time tscl 45 ns v dd = 2.7v to 5.5v 500 ns v dd = 1.8v to 2.7v 73 setup time of sdi input to sck edge t di v2sch 10 ns 74 hold time of sdi input from sck edge tsch2 di l2 0 n s 77 cs inactive (v ih ) to sdo output hi-impedance tcsh2 do z 50 ns note 1 80 sdo data output valid after sck edge tscl2 do v 70 ns v dd = 2.7v to 5.5v 170 ns v dd = 1.8v to 2.7v 83 cs inactive (v ih ) after sck edge tsch2csi 100 ns v dd = 2.7v to 5.5v 1m s v dd = 1.8v to 2.7v 84 hold time of cs inactive (v ih ) to cs active (v il or v ihh ) tcsa2csi 50 ns note 1: this specification by design. cs sck sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 sdi msb lsb bit6 - - - - - -1 msb in bit6 - - - -1 lsb in 83 84 v ih v il v ihh v ih downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 12 ? 2008 microchip technology inc. figure 1-2: spi timing waveform (mode = 00 ). table 1-2: spi requirements (mode = 00 ) # characteristic symbol min max units conditions sck input frequency f sck 1 0m h z v dd = 2.7v to 5.5v 1m h z v dd = 1.8v to 2.7v 70 cs active (v il or v ihh ) to sck input tcsa2sch 60 ns 71 sck input high time tsch 45 ns v dd = 2.7v to 5.5v 500 ns v dd = 1.8v to 2.7v 72 sck input low time tscl 45 ns v dd = 2.7v to 5.5v 500 ns v dd = 1.8v to 2.7v 73 setup time of sdi input to sck edge t di v2sch 10 ns 74 hold time of sdi input from sck edge tsch2 di l2 0 n s 77 cs inactive (v ih ) to sdo output hi-impedance tcsh2 do z 5 0n s note 1 80 sdo data output valid after sck edge tscl2 do v 7 0n sv dd = 2.7v to 5.5v 170 ns v dd = 1.8v to 2.7v 82 sdo data output valid after cs active (v il or v ihh ) tssl2dov 70 ns 83 cs inactive (v ih ) after sck edge tsch2csi 100 ns v dd = 2.7v to 5.5v 1m s v dd = 1.8v to 2.7v 84 hold time of cs inactive (v ih ) to cs active (v il or v ihh ) tcsa2csi 50 ns note 1: this specification by design. cs scksdo sdi 70 71 72 82 sdi 74 75, 76 msb bit6 - - - - - -1 lsb 77 msb in bit6 - - - -1 lsb in 80 83 84 73 v ih v il v ihh v ih downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 13 mcp414x/416x/424x/426x table 1-3: spi requirements for sdi/sd o multiplexed (read operation only) (2) characteristic symbol min max units conditions sck input frequency f sck 2 5 0k h zv dd = 2.7v to 5.5v cs active (v il or v ihh ) to sck input tcsa2sch 60 ns sck input high time tsch 1.8 us sck input low time tscl 1.8 ns setup time of sdi input to sck edge t di v2sch 40 ns hold time of sdi input from sck edge tsch2 di l4 0 n s cs inactive (v ih ) to sdo output hi-impedance tcsh2 do z 50 ns note 1 sdo data output valid after sck edge tscl2 do v1 . 6u s sdo data output valid after cs active (v il or v ihh ) tssl2dov 50 ns cs inactive (v ih ) after sck edge tsch2csi 100 ns hold time of cs inactive (v ih ) to cs active (v ii or v ihh ) tcsa2csi 50 ns note 1: this specification by design 2: this table is for the devices where the spis sdi and sdo pins are multiplexed (sdi/sdo) and a read command is issued. this is not required for sdi/sdo operation with the increment, decrement, or write commands. this data rate can be increased by having external pull-up resistors to increase the rising edges of each bit. downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 14 ? 2008 microchip technology inc. temperature characteristics electrical specifications: unless otherwise indicated, v dd = +2.7v to +5.5v, v ss =gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 +125 c operating temperature range t a -40 +125 c storage temperature range t a -65 +150 c thermal package resistances thermal resistance, 8l-msop ja 2 1 1 c / w thermal resistance, 8l-pdip ja 89.3 c/w thermal resistance, 8l-soic ja 149.5 c/w thermal resistance, 8l-dfn (3x3) ja 6 0 c / w thermal resistance, 10l-dfn (3x3) ja 5 7 c / w thermal resistance, 10l-msop ja 2 0 2 c / w thermal resistance, 14l-pdip ja 7 0 c / w thermal resistance, 14l-soic ja 95.3 c/w thermal resistance, 14l-tssop ja 1 0 0 c / w thermal resistance, 16l-qfn ja 4 3 c / w downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 15 mcp414x/416x/424x/426x 2.0 typical performance curves note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-1: device current (i dd ) vs. spi frequency (f sck ) and ambient temperature (v dd = 2.7v and 5.5v). figure 2-2: device current (i shdn ) and v dd . (cs = v dd ) vs. ambient temperature. figure 2-3: write current (i write ) vs. ambient temperature and v dd . figure 2-4: cs pull-up/pull-down resistance (r cs ) and current (i cs ) vs. cs input voltage (v cs ) (v dd = 5.5v). figure 2-5: cs high input entry/exit threshold vs. ambient temperature and v dd . note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purpose s only. the performance characteristics listed herein are not tested or guaranteed. in so me graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power suppl y range) and therefore outs ide the warranted range. 0 50 100 150 200 250 300 350 400 450 500 550 600 650 0.00 2.00 4.00 6.00 8.00 10.00 12.00 f sck (mhz) operating current (i dd ) (a) 2.7v -40c 2.7v 25c 2.7v 85c 2.7v 125c 5.5v -40c 5.5v 25c 5.5v 85c 5.5v 125c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -40 25 85 125 ambient temperature (c) standby current (istby) (a) 5.5v 2.7v 300.0 400.0 500.0 600.0 700.0 800.0 900.0 -40 25 85 125 ambient temperature (c) ee write current (iwrite) (a) 5.5v 0 50 100 150 200 250 2345678910 v cs (v) r cs (kohms) -1000 -800 -600 -400 -200 0 200 400 600 800 1000 i cs (a) i cs r cs 0 2 4 6 8 10 12 -40-20 0 20406080100120 ambient temperature (c) cs v pp threshold (v) 2.7v exit 5.5v exit 2.7v entry 5.5v entry downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 16 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-6: 5k pot mode C r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-7: 5k pot mode C r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-8: 5k C nominal resistance ( ) vs. ambient temperature and v dd . figure 2-9: 5k rheo mode C r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-10: 5k rheo mode C r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-11: 5k C r wb ( ) vs. wiper setting and ambient temperature. 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl -40c 25c 85c r w 125c 5050 5100 5150 5200 5250 5300 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 2.7v 5.5v 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -1.25 -0.75 -0.25 0.25 0.75 1.25 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -2 0 2 4 6 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 0 1000 2000 3000 4000 5000 6000 0 32 64 96 128 160 192 224 256 wiper setting (decimal) r wb (ohms) -40c 25c 85c 125c downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 17 mcp414x/416x/424x/426x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-12: 5k C low-voltage decrement wiper settling time (v dd = 2.7v) (1 s/div). figure 2-13: 5k C low-voltage decrement wiper settling time (v dd = 5.5v) (1 s/div). figure 2-14: 5k C power-up wiper response time (20 ms/div). figure 2-15: 5k C low-voltage increment wiper settling time (v dd = 2.7v) (1 s/div). figure 2-16: 5k C low-voltage increment wiper settling time (v dd = 5.5v) (1 s/div). downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 18 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-17: 10 k pot mode C r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-18: 10 k pot mode C r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-19: 10 k C nominal resistance ( ) vs. ambient temperature and v dd . figure 2-20: 10 k rheo mode C r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-21: 10 k rheo mode C r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-22: 10 k C r wb ( ) vs. wiper setting and ambient temperature. 20 40 60 80 100 120 0 25 50 75 100 125 150 175 200 225 250 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 10000 10050 10100 10150 10200 10250 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 5.5v 2.7v 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -1 -0.5 0 0.5 1 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 25 50 75 100 125 150 175 200 225 250 wiper setting (decimal) wiper resistance (r w ) (ohms) -2 -1 0 1 2 3 4 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 0 2000 4000 6000 8000 10000 12000 0 32 64 96 128 160 192 224 256 wiper setting (decimal) r wb (ohms) -40c 25c 85c 125c downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 19 mcp414x/416x/424x/426x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-23: 10 k C low-voltage decrement wiper settling time (v dd = 2.7v) (1 s/div). figure 2-24: 10 k C low-voltage decrement wiper settling time (v dd = 5.5v) (1 s/div). figure 2-25: 10 k C low-voltage increment wiper settling time (v dd = 2.7v) (1 s/div). figure 2-26: 10 k C low-voltage increment wiper settling time (v dd = 5.5v) (1 s/div). downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 20 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-27: 50 k pot mode C r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-28: 50 k pot mode C r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-29: 50 k C nominal resistance ( ) vs. ambient temperature and v dd . figure 2-30: 50 k rheo mode C r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-31: 50 k rheo mode C r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-32: 50 k C r wb ( ) vs. wiper setting and ambient temperature. 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 49400 49600 49800 50000 50200 50400 50600 50800 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 2.7v 5.5v 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 0 10000 20000 30000 40000 50000 60000 0 32 64 96 128 160 192 224 256 wiper setting (decimal) r wb (ohms) -40c 25c 85c 125c downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 21 mcp414x/416x/424x/426x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-33: 50 k C low-voltage decrement wiper settling time (v dd = 2.7v) (1 s/div). figure 2-34: 50 k C low-voltage decrement wiper settling time (v dd = 5.5v) (1 s/div). figure 2-35: 50 k C low-voltage increment wiper settling time (v dd = 2.7v) (1 s/div). figure 2-36: 50 k C low-voltage increment wiper settling time (v dd = 5.5v) (1 s/div). downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 22 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-37: 100 k pot mode C r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-38: 100 k pot mode C r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-39: 100 k C nominal resistance ( ) vs. ambient temperature and v dd . figure 2-40: 100 k rheo mode C r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-41: 100 k rheo mode C r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-42: 100 k C r wb ( ) vs. wiper setting and ambient temperature. 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.2 -0.1 0 0.1 0.2 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 99000 99500 100000 100500 101000 101500 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 5.5v 2.7v 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (rw) (ohms) -0.6 -0.4 -0.2 0 0.2 0.4 0.6 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 0 20000 40000 60000 80000 100000 120000 0 32 64 96 128 160 192 224 256 wiper setting (decimal) rwb (ohms) -40c 25c 85c 125c downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 23 mcp414x/416x/424x/426x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-43: 100 k C low-voltage decrement wiper settling time (v dd = 2.7v) (1 s/div). figure 2-44: 100 k C low-voltage decrement wiper settling time (v dd = 5.5v) (1 s/div). figure 2-45: 100 k C power-up wiper response time (1 s/div). figure 2-46: 100 k C low-voltage increment wiper settling time (v dd = 2.7v) (1 s/div). downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 24 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-47: resistor network 0 to resistor network 1 r ab (5 k ) mismatch vs. v dd and temperature. figure 2-48: resistor network 0 to resistor network 1 r ab (10 k ) mismatch vs. v dd and temperature. figure 2-49: resistor network 0 to resistor network 1 r ab (50 k ) mismatch vs. v dd and temperature. figure 2-50: resistor network 0 to resistor network 1 r ab (100 k ) mismatch vs. v dd and temperature. 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -40 0 40 80 120 temperature (c) % 5.5v 3.0v -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 -40 0 40 80 120 temperature (c) % 5.5v 3.0v 0 0.02 0.04 0.06 0.08 0.1 0.12 -40 0 40 80 120 temperature (c) % 5.5v 3.0v -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 -40 10 60 110 temperature (c) % 5.5v 3.0v downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 25 mcp414x/416x/424x/426x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-51: v ih (sdi, sck, cs , wp , and shdn ) vs. v dd and temperature. figure 2-52: v il (sdi, sck, cs , wp , and shdn ) vs. v dd and temperature. figure 2-53: i oh (sdo) vs. v dd and temperature. figure 2-54: i ol (sdo) vs. v dd and temperature. 1 1.2 1.4 1.6 1.8 2 2.2 2.4 -40 0 40 80 120 temperature (c) v ih (v) 5.5v 2.7v 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -40 0 40 80 120 temperature (c) v il (v) 5.5v 2.7v -45 -40 -35 -30 -25 -20 -15 -10 -5 0 -40 0 40 80 120 temperature (c) i oh (ma) 5.5v 2.7v 0 5 10 15 20 25 30 35 40 45 50 -40 0 40 80 120 temperature (c) i ol (ma) 5.5v 2.7v downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 26 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd =5v, v ss = 0v. figure 2-55: nominal eeprom write cycle time vs. v dd and temperature. figure 2-56: por/bor trip point vs. v dd and temperature. figure 2-57: sck input frequency vs. voltage and temperature. 2.1 test circuits figure 2-58: -3 db gain vs. frequency test. 3.0 3.2 3.4 3.6 3.8 4.0 4.2 -40 0 40 80 120 temperature (c) t wc (ms) 0 0.2 0.4 0.6 0.8 1 1.2 -40 0 40 80 120 temperature (c) v dd (v) 2.7v 5.5v 12.0 12.5 13.0 13.5 14.0 14.5 15.0 -40 0 40 80 120 temperature (c) fsck (mhz) 2.7v 5.5v + - v out 2.5v dc +5v ab w offset gnd v in downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 27 mcp414x/416x/424x/426x 3.0 pin descriptions the descriptions of the pins are listed in ta b l e 3 - 1 . additional descriptions of the device pins follows. table 3-1: pinout description for the mcp414x/416x/424x/426x pin weak pull-up/ down (note 2) standard function single dual symbol i/o buffer type rheo pot (1) rheo pot 8l 8l 10l 14l 16l 11111 6 c s i hv w/st smart spi chip select input 2 2 2 2 1 sck i hv w/st smart spi clock input 3 3 3 2 sdi i hv w/st smart spi serial data input 3 sdi/sdo i/o hv w/st smart spi serial data input/output (note 1, note 3) 44443 , 4 v ss p ground 5 5 5 p1b a analog no potentiometer 1 terminal b 6 6 6 p1w a analog no potentiometer 1 wiper terminal 7 7 p1a a analog no potentiometer 1 terminal a 5 8 8 p0a a analog no potentiometer 0 terminal a 5 6 7 9 9 p0w a analog no potentiometer 0 wiper terminal 6 7 8 10 10 p0b a analog no potentiometer 0 terminal b 1 11 2 w p i i smart hardware eeprom write protect 12 13 shdn i hv w/st smart hardware shutdown 7 9 13 14 sdo o o no spi serial data out 8 8 10 14 15 v dd p positive power supply input 1 1 n c no connection 991 11 7 e p exposed pad. (note 4) legend: hv w/st = high voltage tolerant input (with schmidtt trigger input) a = analog pins (potentiometer terminals) i = digital input (high z) o = digital output i/o = input / output p = power note 1: the 8-lead single potentiometer devices are pin limited so the sdo pin is multiplexed with the sdi pin (sdi/sdo pin). after the address/command (first 6-bi ts) are received, if a valid read command has been requested, the sdo pin starts driving the requested read data onto the sdi/sdo pin. 2: the pins smart pull-up shuts off while the pin is forced low. this is done to reduce the standby and shut- down current. 3: the sdo is an open drain output, which uses the inter nal smart pull-up. the sdi input data rate can be at the maximum spi frequency. the sdo output data rate will be limited by t he speed of the pull-up, customers can increase the rate wit h external pull-up resistors. 4: the dfn and qfn packages have a contact on the bott om of the package. this contact is conductively connected to the die substrate, and therefore should be unconnected or connected to the same ground as the devices v ss pin. downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 28 ? 2008 microchip technology inc. 3.1 chip select (cs ) the cs pin is the serial interfaces chip select input. forcing the cs pin to v il enables the serial commands. forcing the cs pin to v ihh enables the high-voltage serial commands. 3.2 serial data in (sdi) the sdi pin is the serial interfaces serial data in pin. this pin is connected to the host controllers sdo pin. 3.3 serial data in / serial data out (sdi/sdo) on the mcp41x1 devices, pin-out limitations do not allow for individual sdi and sdo pins. on these devices, the sdi and sdo pins are multiplexed. the mcp41x1 serial interface knows when the pin needs to change from being an input (sdi) to being an output (sdo). the host controllers sdo pin must be properly protected from a drive conflict. 3.4 ground (v ss ) the v ss pin is the device ground reference. 3.5 potentiometer terminal b the terminal b pin is connec ted to the internal potenti- ometers terminal b. the potentiometers terminal b is the fixed connection to the zero scale wiper value of the digital potentiome- ter. this corresponds to a wiper value of 0x00 for both 7-bit and 8-bit devices. the terminal b pin does not have a polarity relative to the terminal w or a pins. the terminal b pin can support both positive and negative current. the voltage on terminal b must be between v ss and v dd . mcp42xx devices have two terminal b pins, one for each resistor network. 3.6 potentiometer wiper (w) terminal the terminal w pin is connected to the internal potenti- ometers terminal w (the wiper). the wiper terminal is the adjustable terminal of the digital potentiometer. the terminal w pin does not have a polarity relative to terminals a or b pins. the terminal w pin can support both positive and negative current. the voltage on terminal w must be between v ss and v dd . mcp42xx devices have two terminal w pins, one for each resistor network. 3.7 potentiometer terminal a the terminal a pin is available on the mcp4xx1 devices, and is connected to the internal potentiome- ters terminal a. the potentiometers terminal a is the fixed connection to the full scale wiper value of the digital potentiometer. this corresponds to a wiper value of 0x100 for 8-bit devices or 0x80 for 7-bit devices. the terminal a pin does not have a polarity relative to the terminal w or b pins. the terminal a pin can support both positive and negative current. the voltage on terminal a must be between v ss and v dd . the terminal a pin is not available on the mcp4xx2 devices, and the internally terminal a signal is floating. mcp42x1 devices have two terminal a pins, one for each resistor network. 3.8 write protect (wp ) the wp pin is used to force the non-volatile memory to be write protected. 3.9 shutdown (shdn ) the shdn pin is used to force the resistor network terminals into the hardware shutdown state. 3.10 serial data out (sdo) the sdo pin is the serial interfaces serial data out pin. this pin is connected to t he host controllers sdi pin. this pin allows the host controller to read the digital potentiometers registers, or monitor the state of the command error bit. 3.11 positive power supply input (v dd ) the v dd pin is the devices positive power supply input. the input power supply is relative to v ss . while the device v dd < v min (2.7v), the electrical performance of the device may not meet the data sheet specifications. 3.12 no connection (nc) those pins should be either connected to v dd or v ss . 3.13 exposed pad (ep) this pad is conductively connected to the device's substrate. this pad should be tied to the same potential as the v ss pin (or left unconnected). this pad could be used to assist as a heat sink for the device when connected to a pcb heat sink. downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 29 mcp414x/416x/424x/426x 4.0 functional overview this data sheet covers a family of thirty-two digital potentiometer and rheost at devices that will be referred to as mcp4xxx. the mcp4xx1 devices are the potentiometer configuration, while the mcp4xx2 devices are the rheostat configuration. as the device block diagram shows, there are four main functional blocks. these are: por/bor operation memory map resistor network serial interface (spi) the por/bor operation an d the memory map are discussed in this section and the resistor network and spi operation are described in their own sections. the device commands commands are discussed in section 7.0 . 4.1 por/bor operation the power-on reset is the case where the device is having power applied to it from v ss . the brown-out reset occurs when a device had power applied to it, and that power (voltage) drops below the specified range. the devices ram retention voltage (v ram ) is lower than the por/bor voltage trip point (v por /v bor ). the maximum v por /v bor voltage is less then 1.8v. when v por /v bor < v dd < 2.7v, the electrical performance may not meet the data sheet specifications. in this region, the device is capable of reading and writing to its eeprom and incrementing, decrementing, reading and writing to its volatile memory if the proper serial command is executed. 4.1.1 power-on reset when the device powers up, the device v dd will cross the v por /v bor voltage. once the v dd voltage crosses the v por /v bor voltage the following happens: volatile wiper register is loaded with value in the corresponding non-volatile wiper register the tcon register is loaded its default value the device is capable of digital operation 4.1.2 brown-out reset when the device powers down, the device v dd will cross the v por /v bor voltage. once the v dd voltage decreases below the v por /v bor voltage the following happens: serial interface is disabled eeprom writes are disabled if the v dd voltage decreases below the v ram voltage the following happens: volatile wiper registers may become corrupted tcon register may become corrupted as the voltage recovers above the v por /v bor voltage see section 4.1.1 power-on reset . serial commands not completed due to a brown-out condition may cause the memory location (volatile and non-volatile) to become corrupted. 4.2 memory map the device memory is 16 locations that are 9-bits wide (16x9 bits). this memory space contains both volatile and non-volatile locations (see table 4-1 ). table 4-1: memory map address function memory type 00h volatile wiper 0 ram 01h volatile wiper 1 ram 02h non-volatile wiper 0 eeprom 03h non-volatile wiper 1 eeprom 04h volatile tcon register ram 05h status register ram 06h data eeprom eeprom 07h data eeprom eeprom 08h data eeprom eeprom 09h data eeprom eeprom 0ah data eeprom eeprom 0bh data eeprom eeprom 0ch data eeprom eeprom 0dh data eeprom eeprom 0eh data eeprom eeprom 0fh data eeprom eeprom downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 30 ? 2008 microchip technology inc. 4.2.1 non-volatile memory (eeprom) this memory can be grouped into two uses of non-volatile memory. these are: general purpose registers non-volatile wiper registers the non-volatile wipers starts functioning below the devices v por /v bor trip point. 4.2.1.1 general purpose registers these locations allow the user to store up to 10 (9-bit) locations worth of information. 4.2.1.2 non-volatile wiper registers these locations contain the wiper values that are loaded into the corresponding volatile wiper register whenever the device has a por/bor event. there are up to two registers, one for each resistor network. the non-volatile wiper register enables stand-alone operation of the device (wit hout microcontroller control) after being programmed to the desired value. 4.2.1.3 factory initializ ation of non-volatile memory (eeprom) the non-volatile wiper values will be initialized to mid-scale value. this is shown in table 4-2 . the general purpose eeprom memory will be programmed to a default value of 0xff. it is good practice in the manufacturing flow to configure the device to your desired settings. table 4-2: default factory settings selection 4.2.1.4 special features there are 3 non-volatile bi ts that are not directly mapped into the address space. these bits control the following functions: eeprom write protect wiperlock technology for non-volatile wiper 0 wiperlock technology for non-volatile wiper 1 the operation of wiperlock technology is discussed in section 5.3 . the state of the wl0, wl1, and wp bits is reflected in the status register (see register 4-1 ). eeprom write protect all internal eeprom memory can be write protected. when eeprom memory is write protected, write commands to the internal eeprom are prevented. write protect (wp ) can be enabled/disabled by two methods. these are: external wp hardware pin (mcp42x1 devices only) non-volatile configuration bit high voltage commands are required to enable and disable the nonvolatile wp bit. these commands are shown in section 7.9 modify write protect or wip- erlock technology (high voltage) . to write to eeprom, both the external wp pin and the internal wp eeprom bit mu st be disabled. write protect does not block commands to the volatile registers. 4.2.2 volatile memory (ram) there are four volatile me mory locations. these are: volatile wiper 0 volatile wiper 1 (dual resistor network devices only) status register terminal control (tcon) register the volatile memory starts functioning at the ram retention voltage (v ram ). resistance code typical r ab value default por wiper setting wiper code wiperlock? technology and write protect setting 8-bit 7-bit -502 5.0 k mid-scale 80h 40h disabled -103 10.0 k mid-scale 80h 40h disabled -503 50.0 k mid-scale 80h 40h disabled -104 100.0 k mid-scale 80h 40h disabled downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 31 mcp414x/416x/424x/426x 4.2.2.1 status (status) register this register contains 5 status bits. these bits show the state of the wiperlock bits, the shutdown bit the write protect bit, and if an eeprom write cycle is active. the status register can be accessed via the read commands. register 4-1 describes each status register bit. the status register is placed at address 05h. register 4-1: status register r-1 r-1 r-1 r-1 r-0 r-x r-x r-x r-x d8:d5 eewa wl1 (1) wl0 (1) shdn wp (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 8-5 d8:d5: reserved. forced to 1 bit 4 eewa: eeprom write active status bit this bit indicates if the eeprom write cycle is occurring. 1 = an eeprom write cycle is currently occurring. only serial commands to the volatile memory locations are allowed (addresses 00h, 01h, 04h, and 05h) 0 = an eeprom write cycle is not currently occurring bit 3 wl1: wiperlock status bit for resistor network 1 (refer to section 5.3 wiperlock? technology for further information) wiperlock (wl) prevents the volatile and non-volatile wiper 1 addresses and the tcon register bits r1hw, r1a, r1w, and r1b from being written to. high voltage commands are required to enable and disable wiperlock technology. 1 = wiper and tcon register bits r1hw, r1a, r1w, and r1b of resistor network 1 (pot 1) are locked (write protected) 0 = wiper and tcon of resistor network 1 (pot 1) can be modified note: the wl1 bit always reflects the result of the last programming cycle to the non-volatile wl1 bit. after a por or bor event, the wl1 bit is loaded with the non-volatile wl1 bit value. bit 2 wl0: wiperlock status bit for resistor network 0 (refer to section 5.3 wiperlock? technology for further information) the wiperlock technology bits (wlx) prevents the volatile and non-volatile wiper 0 addresses and the tcon register bits r0hw, r0a, r0w, and r0b from being written to. high voltage commands are required to enable and disable wiperlock technology. 1 = wiper and tcon register bits r0hw, r0a, r0w, and r0b of resistor network 0 (pot 0) are locked (write protected) 0 = wiper and tcon of resistor network 0 (pot 0) can be modified note: the wl0 bit always reflects the result of the last programming cycle to the non-volatile wl0 bit. after a por or bor event, the wl0 bit is loaded with the non-volatile wl0 bit value. bit 1 shdn: hardware shutdown pin status bit (refer to section 5.4 shutdown for further information) this bit indicates if the hardware shutdown pin (shdn ) is low. a hardware shutdown disconnects the terminal a and forces the wiper (terminal w) to terminal b (see figure 5-2 ). while the device is in hardware shutdown (the shdn pin is low) the serial interface is operational so the status register may be read. 1 = mcp4xxx is in the ha rdware shutdown state 0 = mcp4xxx is not in the hardware shutdown state note 1: requires a high voltage command to modify the state of th is bit (for non-volatile devices only). this bit is not directly written, but reflects the system state (for this feature). downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 32 ? 2008 microchip technology inc. bit 0 wp: eeprom write protect status bit (refer to section eeprom write protect for further information) this bit indicates the status of the write protection on the eeprom memory. when write protect is enabled, writes to all non-volati le memory are prevented. this includes the gener al purpose eeprom memory, and the non-volatile wiper registers. write protect does not block modification of the volatile wiper register values or the volatile tcon re gister value (via increment, decrement, or write commands). this status bit is an or of the devices write protect pin (wp ) and the internal non-volatile wp bit. high voltage commands are require d to enable and disable t he internal wp eeprom bit. 1 = eeprom memory is write protected 0 = eeprom memory can be written register 4-1: status register (continued) note 1: requires a high voltage command to modify the state of th is bit (for non-volatile devices only). this bit is not directly written, but reflects the system state (for this feature). downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 33 mcp414x/416x/424x/426x 4.2.2.2 terminal contro l (tcon) register this register contains 8 control bits. four bits are for wiper 0, and four bits are for wiper 1. register 4-2 describes each bit of the tcon register. the state of each resistor network terminal connection is individually controlled. that is, each terminal connection (a, b and w) can be individually connected/ disconnected from the resistor network. this allows the system to minimize the currents through the digital potentiometer. the value that is written to this register will appear on the resistor network terminals when the serial command has completed. when the wl1 bit is enabled, writes to the tcon register bits r1hw, r1a, r1w, and r1b are inhibited. when the wl0 bit is enabled, writes to the tcon register bits r0hw, r0a, r0w, and r0b are inhibited. on a por/bor this register is loaded with 1ffh (9-bits), for all terminals connected. the hostcontroller needs to detect the por/bor event and then update the volatile tcon register value. downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 34 ? 2008 microchip technology inc. register 4-2: tcon bits (1, 2) r-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 d8 r1hw r1a r1w r1b r0hw r0a r0w r0b bit 8 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 8 d8: reserved. forced to 1 bit 7 r1hw: resistor 1 hardware configuration control bit this bit forces resistor 1 into the shut down configuration of the hardware pin 1 = resistor 1 is not forced to the hardware pin shutdown configuration 0 = resistor 1 is forced to the har dware pin shutdown configuration bit 6 r1a: resistor 1 terminal a (p1a pin) connect control bit this bit connects/disconnects the resistor 1 terminal a to the resistor 1 network 1 = p1a pin is connected to the resistor 1 network 0 = p1a pin is disconnected from the resistor 1 network bit 5 r1w: resistor 1 wiper (p1w pin) connect control bit this bit connects/disconnects the resist or 1 wiper to the resistor 1 network 1 = p1w pin is connected to the resistor 1 network 0 = p1w pin is disconnected from the resistor 1 network bit 4 r1b: resistor 1 terminal b (p1b pin) connect control bit this bit connects/disconnects the resistor 1 terminal b to the resistor 1 network 1 = p1b pin is connected to the resistor 1 network 0 = p1b pin is disconnected from the resistor 1 network bit 3 r0hw: resistor 0 hardware configuration control bit this bit forces resistor 0 into the shut down configuration of the hardware pin 1 = resistor 0 is not forced to the hardware pin shutdown configuration 0 = resistor 0 is forced to the har dware pin shutdown configuration bit 2 r0a: resistor 0 terminal a (p0a pin) connect control bit this bit connects/disconnects the resistor 0 terminal a to the resistor 0 network 1 = p0a pin is connected to the resistor 0 network 0 = p0a pin is disconnected from the resistor 0 network bit 1 r0w: resistor 0 wiper (p0w pin) connect control bit this bit connects/disconnects the resist or 0 wiper to the resistor 0 network 1 = p0w pin is connected to the resistor 0 network 0 = p0w pin is disconnected from the resistor 0 network bit 0 r0b: resistor 0 terminal b (p0b pin) connect control bit this bit connects/disconnects the resistor 0 terminal b to the resistor 0 network 1 = p0b pin is connected to the resistor 0 network 0 = p0b pin is disconnected from the resistor 0 network note 1: the hardware shdn pin (when active) overrides the st ate of these bits. when the shdn pin returns to the inactive state, the tcon register will c ontrol the state of the terminals. the shdn pin does not modify the state of the tcon bits. 2: these bits do not affect the wiper register values. downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 35 mcp414x/416x/424x/426x 5.0 resistor network the resistor network has either 7-bit or 8-bit resolution. each re sistor network allows zero scale to full scale connections. figure 5-1 shows a block diagram for the resistive network of a device. the resistor network is made up of several parts. these include: resistor ladder wiper shutdown (terminal connections) devices have either one or two resistor networks, these are referred to as pot 0 and pot 1. figure 5-1: resistor block diagram. 5.1 resistor ladder module the resistor ladder is a series of equal value resistors (r s ) with a connection point (tap) between the two resistors. the total number of resistors in the series (ladder) determines the r ab resistance (see figure 5-1 ). the end points of the resistor ladder are connected to analog switches which are connected to the device terminal a and terminal b pins. the r ab (and r s ) resistance has small va riations over voltage and temperature. for an 8-bit device, there are 256 resistors in a string between terminal a and terminal b. the wiper can be set to tap onto any of these 256 resistors thus providing 257 possible settings (including terminal a and terminal b). for a 7-bit device, there are 128 resistors in a string between terminal a and terminal b. the wiper can be set to tap onto any of these 128 resistors thus providing 129 possible settings (including terminal a and terminal b). equation 5-1 shows the calculation for the step resistance. equation 5-1: r s calculation r s a r s r s r s b 257 256 255 10 r w (1) w (01h) analog mux r w (1) (00h) r w (1) (feh) r w (1) (ffh) r w (1) (100h) note 1: the wiper resistance is dependent on several factors including, wiper code, device v dd , terminal voltages (on a, b, and w), and temperature. also for the same conditions, each tap selection resistance has a small variation. this r w variation has greater effects on some specifications (such as inl) for the smaller resistance devices (5.0 k ? ) compared to larger resistance devices (100.0 k ? ). r ab 8-bit n = 128 127 126 10 (01h) (00h) (7eh) (7fh) (80h) 7-bit n = r s r ab 256 () ------------- = r s r ab 128 () ------------- - = 8-bit device 7-bit device downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 36 ? 2008 microchip technology inc. 5.2 wiper each tap point (between the r s resistors) is a connection point for an analog switch. the opposite side of the analog switch is connected to a common signal which is connected to the terminal w (wiper) pin. a value in the volatile wiper register selects which analog switch to close, connecting the w terminal to the selected node of the resistor ladder. the wiper can connect directly to terminal b or to terminal a. a zero-scale connections, connects the terminal w (wiper) to terminal b (wiper setting of 000h). a full-scale connections, connects the terminal w (wiper) to terminal a (wip er setting of 100h or 80h). in these configurations the only resistance between the terminal w and the other terminal (a or b) is that of the analog switches. a wiper setting value greater than full scale (wiper setting of 100h for 8-bit device or 80h for 7-bit devices) will also be a full scale setting (terminal w (wiper) connected to terminal a). ta b l e 5 - 1 illustrates the full wiper setting map. equation 5-2 illustrates the calculation used to deter- mine the resistance between the wiper and terminal b. equation 5-2: r wb calculation table 5-1: volatile wiper value vs. wiper position map 5.3 wiperlock? technology the mcp4xxx devices wiperlock technology allows application-specific calibrati on settings to be secured in the eeprom without requiring the use of an additional write-protect pin. there are two wiperlock technology configuration bits (wl0 and wl1). these bits prevent the non-volatile and volatile addresses and bits for the specified resistor netw ork from being written. the wiperlock technology prevents the serial commands from doing the following: changing a volatile wiper value writing to a non-volatile wiper memory location changing the volatile tcon register value for either resistor network 0 or resistor network 1 (potx), the wlx bit controls the following: non-volatile wiper register volatile wiper register volatile tcon register bits rxhw, rxa, rxw, and rxb high voltage commands are required to enable and disable wiperlock. please refer to the modify write protect or wiperlock technology (high voltage) command for operation. 5.3.1 por/bor operation when wiperlock technology enabled the wiperlock technology state is not affected by a por/bor event. a por/bor event will load the volatile wiper register value with the non-volatile wiper register value, refer to section 4.1 . wiper setting properties 7-bit pot 8-bit pot 3ffh 081h 3ffh 101h reserved (full scale (w = a)), increment and decrement commands ignored 080h 100h full scale (w = a), increment commands ignored 07fh 041h 0ffh 081 w = n 040h 080h w = n (mid-scale) 03fh 001h 07fh 001 w = n 000h 000h zero scale (w = b) decrement command ignored r wb r ab n 256 () ------------- -r w + = n = 0 to 256 (decimal) r wb r ab n 128 () ------------- -r w + = n = 0 to 128 (decimal) 8-bit device 7-bit device downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 37 mcp414x/416x/424x/426x 5.4 shutdown shutdown is used to minimize the devices current consumption. the mcp4xxx has two methods to achieve this. these are: hardware shutdown pin (shdn) terminal control register (tcon) the hardware shutdown pin is backwards compatible with the mcp42xxx devices. 5.4.1 hardware shutdown pin (shdn ) the shdn pin is available on the dual potentiometer devices. when the shdn pin is forced active (v il ): the p0a and p1a terminals are disconnected the p0w and p1w terminals are simultaneously connect to the p0b and p1b terminals, respectively (see figure 5-2 ) the serial interface is not disabled, and all serial interface activity is executed any eeprom write cycles are completed the hardware shutdown pin mode does not corrupt the values in the volatile wiper registers nor the tcon register. when the shutdown mode is exited (shdn pin is inactive (v ih )): the device returns to the wiper setting specified by the volatile wiper value the tcon register bits return to controlling the terminal connection state figure 5-2: hardware shutdown resistor networ k configuration. 5.4.2 terminal control register (tcon) the terminal control (tcon) register is a volatile register used to configur e the connection of each resistor network terminal pin (a, b, and w) to the resistor network. this register is shown in register 4-2 . the rxhw bits forces the selected resistor network into the same state as the shdn pin. alternate low power configurations may be achieved with the rxa, rxw, and rxb bits. 5.4.3 interaction of shdn pin and tcon register figure 5-3 shows how the shdn pin signal and the rxhw bit signal interact to control the hardware shutdown of each resistor network (independently). using the tcon bits allows each resistor network (pot 0 and pot 1) to be individually shutdown while the hardware pin forces both resistor networks to be shutdown at the same time. figure 5-3: rxhw bit and shdn pin interaction. a b w resistor network note: when the rxhw bit forces the resistor network into the hardware shdn state, the state of the tcon register rxa, rxw, and rxb bits is overridden (ignored). when the state of the rxhw bit no longer forces the resistor network into the hardware shdn state, the tcon register rxa, rxw, and rxb bits return to control- ling the terminal connection state. in other words, the rxhw bit does not corrupt the state of the rxa, rxw, and rxb bits. shdn (from pin) rxhw (from tcon register) to pot x hardware shutdown control downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 38 ? 2008 microchip technology inc. notes: downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 39 mcp414x/416x/424x/426x 6.0 serial inte rface (spi) the mcp4xxx devices support the spi serial protocol. this spi operates in the slave mode (does not generate the serial clock). the spi interface uses up to four pins. these are: cs - chip select sck - serial clock sdi - serial data in sdo - serial data out typical spi interfaces are shown in figure 6-1 . in the spi interface, the masters output pin is connected to the slaves input pin and the masters input pin is connected to the slaves output pin. the mcp4xxx spis module supports two (of the four) standard spi modes. these are mode 0,0 and 1,1 . the spi mode is determined by the state of the sck pin (v ih or v il ) on the when the cs pin transitions from inactive (v ih ) to active (v il or v ihh ). all spi interface signals are high-voltage tolerant. figure 6-1: typical spi interface block diagram. sdi/sdo sdisdo sdo sdi r 1 (2) mcp41x1 sck sck sdi sdo mcp4xxx sdo sdi sck sck ( master out - slave in (mosi) ) ( master in - slave out (miso) ) host controller host controller typical spi interface connections typical mcp41x1 spi interface connec tions (host controller hardware spi) sdi/sdo sdisdo i/o mcp41x1 i/o sck host controller alternate mcp41x1 spi interface connections (host controller firmware spi) (sdo/sdi) (sck) cs i/o (1) cs i/o (1) cs i/o (1) note 1: if high voltage commands are desired, some type of external circuitry needs to be implemented. 2: r 1 must be sized to ensure v il and v ih of the devices are met. downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 40 ? 2008 microchip technology inc. 6.1 sdi, sdo, sck, and cs operation the operation of the four spi interface pins are discussed in this section. these pins are: sdi (serial data in) sdo (serial data out) sck (serial clock) cs (chip select) the serial interface works on either 8-bit or 16-bit boundaries depending on the selected command. the chip select (cs ) pin frames the spi commands. 6.1.1 serial data in (sdi) the serial data in (sdi) signal is the data signal into the device. the value on this pin is latched on the rising edge of the sck signal. 6.1.2 serial data out (sdo) the serial data out (sdo) signal is the data signal out of the device. the value on this pin is driven on the falling edge of the sck signal. once the cs pin is forced to the active level (v il or v ihh ), the sdo pin will be driv en. the state of the sdo pin is determined by the serial bits position in the command, the command selected, and if there is a command error state (cmderr). 6.1.3 sdi/sdo for device packages that do not have enough pins for both an sdi and sdo pin, the sdi and sdo functionality is multiplexed onto a single i/o pin called sdi/sdo. the sdo will only be driven for the command error bit (cmderr) and during the data bits of a read command (after the memory address and command has been received). 6.1.3.1 sdi/sdo operation figure 6-2 shows a block diagram of the sdi/sdo pin. the sdi signal has an internal smart pull-up. the value of this pull-up determines the frequency that data can be read from the device. an external pull-up can be added to the sdi/sdo pin to improve the rise time and therefore improve the frequency that data can be read. data written on the sdi/sdo pin can be at the maximum spi frequency. on the falling edge of the sck pin during the c0 bit (see figure 7-1 ), the sdi/sdo pin will start outputting the sdo value. the sdo signal overrides the control of the smart pull-up, such that whenever the sdi/sdo pin is outputting data, the sm art pull-up is enabled. the sdi/sdo pin will change from an input (sdi) to an output (sdo) after the state machine has received the address and command bits of the command byte. if the command is a read command, then the sdi/sdo pin will remain an output for the remainder of the command. for any other command, the sdi/sdo pin returns to an input. figure 6-2: serial i/o mux block diagram. note: mcp41x1 devices only . note: to support the high voltage requirement of the sdi function, the sdo function is an open-drain output. note: care must be take to ensure that a drive conflict does not exist between the host controllers sdo pin (or software sdi/sdo pin) and the mcp41x1 sdi/sdo pin (see figure 6-1 ). sdi/sdo sdi sdo control smart pull-up open drain logic downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 41 mcp414x/416x/424x/426x 6.1.4 serial clock (sck) (spi frequency of operation) the spi interface is specified to operate up to 10 mhz. the actual clock rate depends on the configuration of the system and the serial command used. table 6-1 shows the sck frequency for different configurations. table 6-1: sck frequency 6.1.5 the cs signal the chip select (cs ) signal is used to select the device and frame a command sequence. to start a command, or sequence of commands, the cs signal must transition from the inactive state (v ih ) to an active state (v il or v ihh ). after the cs signal has gone active, the sdo pin is driven and the clock bit counter is reset. if an error condition occurs for an spi command, then the command bytes command error (cmderr) bit (on the sdo pin) will be driven low (v il ). to exit the error condition, the user must take the cs pin to the v ih level. when the cs pin returns to the inactive state (v ih ) the spi module resets (including the address pointer). while the cs pin is in the inactive state (v ih ), the serial interface is ignored. this allows the host controller to interface to other spi devices using the same sdi, sdo, and sck signals. the cs pin has an internal pull-up resistor. the resistor is disabled when the voltage on the cs pin is at the v il level. this means that when the cs pin is not driven, the internal pull-up resistor will pull this signal to the v ih level. when the cs pin is driven low (v il ), the resistance becomes very la rge to reduce the device current consumption. the high voltage capability of the cs pin allows high voltage commands. high voltage commands allow the devices wiperlock technology and write protect features to be enabled and disabled. memory type access command read write, increment, decrement non-volatile memory sdi, sdo 10 mhz 10 mhz (2, 3) sdi/sdo (1) 250 khz (4) 10 mhz (2, 3) volatile memory sdi, sdo 10 mhz 10 mhz sdi/sdo (1) 250 khz (4) 10 mhz note 1: mcp41x1 devices only 2: non-volatile memory does not support the increment or decrement command. 3: after a write command, the internal write cycle must complete before the next spi command is received. 4: this is the maximum clock frequency without an external pull-up resistor. note: there is a required delay after the cs pin goes active to the 1st edge of the sck pin. downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 42 ? 2008 microchip technology inc. 6.2 the spi modes the spi module supports two (of the four) standard spi modes. these are mode 0,0 and 1,1. the mode is determined by the state of the sdi pin on the rising edge of the 1st clock bit (of the 8-bit byte). 6.2.1 mode 0,0 in mode 0,0 : sck idle state = low (v il ), data is clocked in on the sdi pin on the rising edge of sck and clocked out on the sdo pin on the falling edge of sck. 6.2.2 mode 1,1 in mode 1,1 : sck idle state = high (v ih ), data is clocked in on the sdi pin on the rising edge of sck and clocked out on the sdo pin on the falling edge of sck. 6.3 spi waveforms figure 6-3 through figure 6-8 show the different spi command waveforms. figure 6-3 and figure 6-4 are read and write commands. figure 6-5 and figure 6-6 are read commands when the sdi and sdo pins are multiplexed on the same pin (sdi/sdo). figure 6-7 and figure 6-8 are increment and decrement commands. the high voltage increment and decrement commands are used to enable and disable wiperlock technology and write protect. figure 6-3: 16-bit commands (write, read) - spi waveform (mode 1,1). figure 6-4: 16-bit commands (write, read) - spi waveform (mode 0,0). cs sck write to sspbuf sdi input sample sdo bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ad3 ad2 ad1 ad0 c1 c0 x d8 d7 d6 d5 d4 d3 d2 d1 d0 v ih v il cmderr bit v ihh cs sck write to sspbuf sdi input sample sdo bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit14 bit13 bit12 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ad3 ad2 ad1 ad0 c1 c0 x d8 d7 d6 d5 d4 d3 d2 d1 d0 v ih v il cmderr bit v ihh downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 43 mcp414x/416x/424x/426x figure 6-5: 16-bit read command for devi ces with sdi/sdo multiplexed - spi waveform (mode 1,1). figure 6-6: 16-bit read command for devi ces with sdi/sdo multiplexed - spi waveform (mode 0,0). cs sck write to sspbuf sdi input sample sdo bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit14 bit13 bit12 ad3 ad2 ad1 ad0 c1 c0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 v ih v il cmderr bit note 1: the sdi pin will read the state of the sdi pin which will be the sdo signal, unless overdriven (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 11 v ihh cs sck write to sspbuf sdi input sample sdo bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit14 bit13 bit12 ad3 ad2 ad1 ad0 c1 c0 d8 d7 d6 d5 d4 d3 d2 d1 d0 x v ih v il cmderr bit note 1: the sdi pin will read the state of the sdi pin which will be the sdo signal, unless overdriven (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 11 v ihh downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 44 ? 2008 microchip technology inc. figure 6-7: 8-bit commands (increment, decrement, modify write protect or wiperlock technology) - spi waveform with pic mcu (mode 1,1). figure 6-8: 8-bit commands (increment, decrement, modify write protect or wiperlock technology) - spi waveform with pic mcu (mode 0,0). bit7 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cs sck write to sspbuf sdi input sample sdo v ih v il ad3 ad2 ad1 ad0 c0 c1 x x 1 = valid command/address 0 = invalid command/address cmderr bit v ihh sck input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write to sspbuf cs v ih v il ad3 ad2 ad1 ad0 c0 c1 x x 1 = valid command/address 0 = invalid command/address cmderr bit v ihh downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 45 mcp414x/416x/424x/426x 7.0 device commands the mcp4xxxs spi command format supports 16 memory address locations and four commands. each command has two modes. these are: normal serial commands high-voltage serial commands normal serial commands are those where the cs pin is driven to v il . with high-voltage serial commands, the cs pin is driven to v ihh . in each mode, there are four possible commands. these commands are shown in table 7-1 . the 8-bit commands ( increment wiper and decre- ment wiper commands) contain a command byte, see figure 7-1 , while 16-bit commands ( read data and write data commands) contain a command byte and a data byte. the command byte contains two data bits, see figure 7-1 . table 7-2 shows the supported commands for each memory location and the corresponding values on the sdi and sdo pins. table 7-3 shows an overview of all the spi commands and their interaction with other device features. 7.1 command byte the command byte has three fields, the address, the command, and 2 data bits, see figure 7-1 . currently only one of the data bits is defined (d8). this is for the write command. the device memory is accessed when the master sends a proper command byte to select the desired operation. the memory location getting accessed is contained in the command bytes ad3:ad0 bits. the action desired is contained in the command bytes c1:c0 bits, see ta b l e 7 - 1 . c1:c0 determines if the desired memory location will be read, written, incremented (wiper setting +1) or decremented (wiper setting -1). the increment and decrement commands are only valid on the volat ile wiper registers, and in high voltage commands to enable/disable wiperlock technology and software write protect. as the command byte is being loaded into the device (on the sdi pin), the devices sdo pin is driving. the sdo pin will output high bits for the first six bits of that command. on the 7th bit, the sdo pin will output the cmderr bit state (see section 7.3 error condi- tion ). the 8th bit state depends on the the command selected. table 7-1: command bit overview figure 7-1: general spi command formats. c1:c0 bit states command # of bits operates on volatile/ non-volatile memory 11 read data 16-bits both 00 write data 16-bits both 01 increment (1) 8-bits volatile only 10 decrement (1) 8-bits volatile only note 1: high voltage increment and decrement commands on select non-volatile memory locations enable/disable wiperlock technology and the software write protect feature. a d 3 a d 2 a d 1 a d 0 c 1 c 0 d 9 d 8 memory command byte data address bits command bits a d 3 a d 2 a d 1 a d 0 c 1 c 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 memory 16-bit command data address bits command bits 0 0 = write data 0 1 = incr 1 0 = decr 1 1 = read data c c 1 0 command bits 8-bit command command byte data byte downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 46 ? 2008 microchip technology inc. table 7-2: memory map and the supported commands address command data (10-bits) (1) spi string (binary) value function mosi (sdi pin) miso (sdo pin) (2) 00h volatile wiper 0 write data nn nnnn nnnn 0000 00nn nnnn nnnn 1111 1111 1111 1111 read data nn nnnn nnnn 0000 11nn nnnn nnnn 1111 111n nnnn nnnn increment wiper 0000 0100 1111 1111 decrement wiper 0000 1000 1111 1111 01h volatile wiper 1 write data nn nnnn nnnn 0001 00nn nnnn nnnn 1111 1111 1111 1111 read data nn nnnn nnnn 0001 11nn nnnn nnnn 1111 111n nnnn nnnn increment wiper 0001 0100 1111 1111 decrement wiper 0001 1000 1111 1111 02h nv wiper 0 write data nn nnnn nnnn 0010 00nn nnnn nnnn 1111 1111 1111 1111 read data nn nnnn nnnn 0010 11nn nnnn nnnn 1111 111n nnnn nnnn hv inc. (wl0 dis) (3) 0010 0100 1111 1111 hv dec. (wl0 en) (4) 0010 1000 1111 1111 03h nv wiper 1 write data nn nnnn nnnn 0011 00nn nnnn nnnn 1111 1111 1111 1111 read data nn nnnn nnnn 0011 11nn nnnn nnnn 1111 111n nnnn nnnn hv inc. (wl1 dis) (3) 0011 0100 1111 1111 hv dec. (wl1 en) (4) 0011 1000 1111 1111 04h (5) volatile tcon register write data nn nnnn nnnn 0100 00nn nnnn nnnn 1111 1111 1111 1111 read data nn nnnn nnnn 0100 11nn nnnn nnnn 1111 111n nnnn nnnn 05h (5) status register read data nn nnnn nnnn 0101 11nn nnnn nnnn 1111 111n nnnn nnnn 06h (5) data eeprom write data nn nnnn nnnn 0110 00nn nnnn nnnn 1111 1111 1111 1111 read data nn nnnn nnnn 0110 11nn nnnn nnnn 1111 111n nnnn nnnn 07h (5) data eeprom write data nn nnnn nnnn 0111 00nn nnnn nnnn 1111 1111 1111 1111 read data nn nnnn nnnn 0111 11nn nnnn nnnn 1111 111n nnnn nnnn 08h (5) data eeprom write data nn nnnn nnnn 1000 00nn nnnn nnnn 1111 1111 1111 1111 read data nn nnnn nnnn 1000 11nn nnnn nnnn 1111 111n nnnn nnnn 09h (5) data eeprom write data nn nnnn nnnn 1001 00nn nnnn nnnn 1111 1111 1111 1111 read data nn nnnn nnnn 1001 11nn nnnn nnnn 1111 111n nnnn nnnn 0ah (5) data eeprom write data nn nnnn nnnn 1010 00nn nnnn nnnn 1111 1111 1111 1111 read data nn nnnn nnnn 1010 11nn nnnn nnnn 1111 111n nnnn nnnn 0bh (5) data eeprom write data nn nnnn nnnn 1011 00nn nnnn nnnn 1111 1111 1111 1111 read data nn nnnn nnnn 1011 11nn nnnn nnnn 1111 111n nnnn nnnn 0ch (5) data eeprom write data nn nnnn nnnn 1100 00nn nnnn nnnn 1111 1111 1111 1111 read data nn nnnn nnnn 1100 11nn nnnn nnnn 1111 111n nnnn nnnn 0dh (5) data eeprom write data nn nnnn nnnn 1101 00nn nnnn nnnn 1111 1111 1111 1111 read data nn nnnn nnnn 1101 11nn nnnn nnnn 1111 111n nnnn nnnn 0eh (5) data eeprom write data nn nnnn nnnn 1110 00nn nnnn nnnn 1111 1111 1111 1111 read data nn nnnn nnnn 1110 11nn nnnn nnnn 1111 111n nnnn nnnn 0fh data eeprom write data nn nnnn nnnn 1111 00nn nnnn nnnn 1111 1111 1111 1111 read data nn nnnn nnnn 1111 11nn nnnn nnnn 1111 111n nnnn nnnn hv inc. (wp dis) (3) 1111 0100 1111 1111 hv dec. (wp en) (4) 1111 1000 1111 1111 note 1: the data memory is only 9-bits wide, so the msb is ignored by the device. 2: all these address/command combinations are valid, so the cmderr bit is set. any other address/command combi- nation is a command error state and the cmderr bit will be clear. 3: disables wiperlock technology for wiper 0 or wiper 1, or disables write protect. 4: enables wiperlock technology for wiper 0 or wiper 1, or enables write protect. 5: reserved addresses : increment or decrement commands are invalid for these addresses. downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 47 mcp414x/416x/424x/426x 7.2 data byte only the read command and the write command use the data byte, see figure 7-1 . these commands concatenate the 8-bits of the data byte with the one data bit (d8) contained in the command byte to form 9-bits of data (d8:d0). the command byte format supports up to 9-bits of data so that the 8-bit resistor network can be set to full scale (100h or greater). this allows wiper connections to terminal a and to terminal b. the d9 bit is currently unused, and corresponds to the position on the sdo data of the cmderr bit. 7.3 error condition the cmderr bit indicates if the four address bits received (ad3:ad0) and the two command bits received (c1:c0) are a valid combination (see table 4-1 ). the cmderr bit is high if the combination is valid and low if the combination is invalid. the command error bit will also be low if a write to a non-volatile address has been specified and another spi command occurs before the cs pin is driven inactive (v ih ). spi commands that do not have a multiple of 8 clocks are ignored. once an error condition has occurred, any following commands are ignored. all following sdo bits will be low until the cmderr condition is cleared by forcing the cs pin to the inactive state (v ih ). 7.3.1 aborting a transmission all spi transmissions must have the correct number of sck pulses to be executed. the command is not executed until the comple te number of clocks have been received. some commands also require the cs pin to be forced inactive (v ih ). if the cs pin is forced to the inactive state (v ih ) the serial interface is reset. partial commands are not executed. spi is more susceptible to noise than other bus protocols. the most likely case is that this noise corrupts the value of the data being clocked into the mcp4xxx or the sck pin is injected with extra clock pulses. this may cause data to be corrupted in the device, or a command error to occur, since the address and command bits were not a valid combination. the extra sck pulse will also cause the spi data (sdi) and clock (sck) to be out of sync. forcing the cs pin to the inactive state (v ih ) resets the serial interface. the spi interface will ignore activity on the sdi and sck pins until the cs pin transition to the active state is detected (v ih to v il or v ih to v ihh ). note 1: when data is not being received by the mcp4xxx, it is recommended that the cs pin be forced to the inactive level (v il ) 2: it is also recommended that long continu- ous command strings should be broken down into single commands or shorter continuous command strings. this reduces the probability of noise on the sck pin corrupting the desired spi commands. downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 48 ? 2008 microchip technology inc. 7.4 continuous commands the device supports the ability to execute commands continuously. while the cs pin is in the active state (v il or v ihh ). any sequence of valid commands may be received. the following example is a valid sequence of events: 1. cs pin driven active (v il or v ihh ). 2. read command. 3. increment command (wiper 0). 4. increment command (wiper 0). 5. decrement command (wiper 1). 6. write command (volatile memory). 7. write command (non-volatile memory). 8. cs pin driven inactive (v ih ). table 7-3: commands note 1: it is recommended that while the cs pin is active, only one type of command should be issued. when changing commands, it is recommended to take the cs pin inactive then force it back to the active state. 2: it is also recommended that long command strings should be broken down into shorter command strings. this reduces the probability of noise on the sck pin corrupting the desired spi command string. command name # of bits writes value in eeprom operates on volatile/ non-volatile memory high voltage (v ihh ) on cs pin? impact on wiperlock or write protect works when wiper is locked? write data 16-bits yes (1) both unlocked (1) no read data 16-bits both unlocked (1) no increment wiper 8-bits volatile only unlocked (1) no decrement wiper 8-bits volatile only unlocked (1) no high voltage write data 16-bits yes both yes unchanged no high voltage read data 16-bits both yes unchanged yes high voltage increment wiper 8-bits volatile only yes unchanged no high voltage decrement wiper 8-bits volatile only yes unchanged no modify write protect or wiper- lock technology (high voltage) - enable 8-bits (2) non-volatile only (2) yes locked/ protected (2) yes modify write protect or wiper- lock technology (high voltage) - disable 8-bits (3) non-volatile only (3) yes unlocked/ unprotected (3) yes note 1: this command will only complete if wiper is unlocked (wiperlock technology is disabled). 2: if the command is executed using address 02h or 03h, then that correspond ing wiper is locked or if with address 0fh, then write protect is enabled. 3: if the command is executed using with address 02h or 03h, then that corresponding wiper is unlocked or if with address 0fh, then write protect is disabled. downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 49 mcp414x/416x/424x/426x 7.5 write data normal and high voltage the write command is a 16-bit command. the write command can be issued to both the volatile and non-volatile memory loca tions. the format of the command is shown in figure 7-2 . a write command to a vo latile memory location changes that location after a properly formatted write command (16-clock) have been received. a write command to a non-volatile memory location will only start a write cycle after a properly formatted write command (16-clock) have been received and the cs pin transitions to the inactive state (v ih ). 7.5.1 single write to volatile memory the write operation re quires that the cs pin be in the active state (v il or v ihh ). typically, the cs pin will be in the inactive state (v ih ) and is driven to the active state (v il ). the 16-bit write command (command byte and data byte) is then clocked in on the sck and sdi pins. once all 16 bits have been received, the specified volatile address is updated. a write will not occur if the write command isnt exactly 16 clocks pulses. this protects against system issues from corrupting the non-volatile memory locations. figure 6-3 and figure 6-4 show possible waveforms for a single write. 7.5.2 single write to non-volatile memory the sequence to write to to a single non-volatile memory location is the same as a single write to volatile memory with the except ion that after the cs pin is driven inactive (v ih ), the eeprom write cycle (t wc ) is started. a write cycle will not start if the write command isnt exactly 16 clocks pulses. this protects against system issues from corrupting the non-volatile memory locations. after the cs pin is driven inactive (v ih ), the serial interface may immediately be re-enabled by driving the cs pin to the active state (v il or v ihh ). during an eeprom write cycl e, only serial commands to volatile memory (addresses 00h, 01h, 04h, and 05h) are accepted. all other serial commands are ignored until the eeprom write cycle (t wc ) completes. this allows the host controller to operate on the volatile wiper registers and the tcon register, and to read the status register. the eewa bit in the status register indicates the status of an eeprom write cycle. once a write command to a non-volatile memory location has been received, no other spi commands should be received before the cs pin transitions to the inactive state (v ih ) or the current spi command will have a command error (cmderr) occur. figure 7-2: write command - sdi and sdo states. note: writes to certain memory locations will be dependant on the state of the wiperlock technology bits and the write protect bit. a d 3 a d 2 a d 1 a d 0 00d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1111111111111111valid address/command combination 111111 0 0 0 0 0 0 0 0 0 0 invalid address/command combination (1) command byte data byte sdisdo note 1: if an error condition occurs (cmderr = l), all following sdo bits will be low until the cmderr condition is cleared (the cs pin is forced to the inactive state). downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 50 ? 2008 microchip technology inc. 7.5.3 continuous writes to volatile memory continuous writes are possible only when writing to the volatile memory registers (address 00h, 01h, and 04h). figure 7-3 shows the sequence for three continuous writes. the writes do not need to be to the same volatile memory address. 7.5.4 continuous writes to non-volatile memory continuous writes to non-volatile memory are not allowed, and attempts to do so will result in a command error (cmderr) condition. figure 7-3: continuous write sequence (volatile memory only). a d 3 a d 2 a d 1 a d 0 00d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1111111*111111111 a d 3 a d 2 a d 1 a d 0 00d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1111111*111111111 a d 3 a d 2 a d 1 a d 0 00d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1111111*111111111 command byte data byte sdisdo note 1: if a command error (cmderr) occurs at this bi t location (*), then all following sdo bits will be driven low until the cs pin is driven inactive (v ih ). downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 51 mcp414x/416x/424x/426x 7.6 read data normal and high voltage the read command is a 16-bit command. the read command can be issued to both the volatile and non-volatile memory loca tions. the format of the command is shown in figure 7-4 . the first 6-bits of the read command determine the address and the command. the 7th clock will output the cmderr bit on the sdo pin. the remaining 9-clocks the device will transmit the 9 data bits (d8:d0) of the specified address (ad3:ad0). figure 7-4 shows the sdi and sdo information for a read command. during a write cycle (write or high voltage write to a non-volatile memory location) the read command can only read the volatile memory locations. by reading the status register (04h), the host controller can determine when the write cycl e has completed (via the state of the eewa bit). 7.6.1 single read the read operation re quires that the cs pin be in the active state (v il or v ihh ). typically, the cs pin will be in the inactive state (v ih ) and is driven to the active state (v il or v ihh ). the 16-bit re ad command (command byte and data byte) is then clocked in on the sck and sdi pins. the sdo pin starts driving data on the 7th bit (cmderr bit) and the addressed data comes out on the 8th through 16th clocks. figure 6-3 through figure 6-6 show possible waveforms for a single read. figure 6-5 and figure 6-6 show the single read waveforms when the sdi and sdo signals are multiplexed on the same pin. for additional information on the multiplexing of these signals, refer to section 6.1.3 sdi/sdo . figure 7-4: read command - sdi and sdo states. a d 3 a d 2 a d 1 a d 0 1 1xxxxxxxxxx 1111111d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 valid address/command combination 1111110000000000attempted non-volatile memory read during non-volatile memory write cycle command byte data byte sdisdo read data downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 52 ? 2008 microchip technology inc. 7.6.2 continuous reads continuous reads allows the devices memory to be read quickly. continuous reads are possible to all memory locations. if a non-vo latile memory write cycle is occurring, then read commands may only access the volatile memory locations. figure 7-5 shows the sequence for three continuous reads. the reads do not need to be to the same memory address. figure 7-5: continuous read sequence. a d 3 a d 2 a d 1 a d 0 1 1xxxxxxxxxx 1111111*d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a d 3 a d 2 a d 1 a d 0 1 1xxxxxxxxxx 1111111*d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a d 3 a d 2 a d 1 a d 0 1 1xxxxxxxxxx 1111111*d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command byte data byte sdisdo note 1: if a command error (cmderr) occurs at this bi t location (*), then all following sdo bits will be driven low until the cs pin is driven inactive (v ih ). downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 53 mcp414x/416x/424x/426x 7.7 increment wiper normal and high voltage the increment command is an 8-bit command. the increment command can only be issued to volatile memory locations. the format of the command is shown in figure 7-6 . an increment command to the volatile memory location changes that location after a properly formatted command (8-clocks) have been received. increment commands provide a quick and easy method to modify the value of the volatile wiper location by +1 with minimal overhead. figure 7-6: increment command - sdi and sdo states. 7.7.1 single increment typically, the cs pin starts at the inactive state (v ih ), but may be already be in the active state due to the completion of another command. figure 6-7 through figure 6-8 show possible waveforms for a single increment. the increment operation requires that the cs pin be in the active state (v il or v ihh ). typically, the cs pin will be in the inactive state (v ih ) and is driven to the active state (v il or v ihh ). the 8-bit increment command (command byte) is then clocked in on the sdi pin by the sck pins. the sdo pin drives the cmderr bit on the 7th clock. the wiper value will increment up to 100h on 8-bit devices and 80h on 7-bit devices. after the wiper value has reached full scale (8-bit =100h, 7-bit =80h), the wiper value will not be incremented further. if the wiper register has a value between 101h and 1ffh, the increment command is disabled. see table 7-4 for additional information on the increment command versus the current volatile wiper value. the increment operations only require the increment command byte while the cs pin is active (v il or v ihh ) for a single increment. after the wiper is incremented to the desired position, the cs pin should be forced to v ih to ensure that unexpected transitions on the sck pin do not cause the wiper setting to change. driving the cs pin to v ih should occur as soon as possible (within device specifications) after the last desired increment occurs. table 7-4: increment operation vs. volatile wiper value note: table 7-2 shows the valid addresses for the increment wiper command. other addresses are invalid. a d 3 a d 2 a d 1 a d 0 01xx 1111111*1 note 1, 2 111111 0 0 note 1, 3 (incr command (n+1) ) sdi sdo command byte note 1: only functions when writing the volatile wiper registers (ad3:ad0) 0h and 1h. 2: valid address/command combination. 3: invalid address/command combination all following sdo bits will be low until the cmderr condition is cleared. (the cs pin is forced to the inactive state). 4: if a command erro r (cmderr) occurs at this bit location (*), then all following sdo bits will be driven low until the cs pin is driven inactive (v ih ). current wiper setting wiper (w) properties increment command operates? 7-bit pot 8-bit pot 3ffh 081h 3ffh 101h reserved (full-scale (w = a)) no 080h 100h full-scale (w = a) no 07fh 041h 0ffh 081 w = n 040h 080h w = n (mid-scale) yes 03fh 001h 07fh 001 w = n 000h 000h zero scale (w = b) yes downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 54 ? 2008 microchip technology inc. 7.7.2 continuous increments continuous increments are possible only when writing to the volatile memory r egisters (address 00h, and 01h). figure 7-7 shows a continuous increment sequence for three continuous writes . the writes do not need to be to the same volatile memory address. when executing an contin uous increment commands, the selected wiper will be altered from n to n+1 for each increment command received. the wiper value will increment up to 100h on 8-bit devices and 80h on 7-bit devices. after the wiper value has reached full-scale (8-bit =100h, 7-bit =80h), the wiper value will not be incremented further. if the wiper register has a value between 101h and 1ffh, the increment command is disabled. increment commands can be sent repeatedly without raising cs until a desired condition is met. the value in the volatile wiper register can be read using a read command and written to the corresponding non-volatile wiper eeprom using a write command. when executing a continuous command string, the increment command can be followed by any other valid command. the wiper terminal will move after the command has been received (8th clock). after the wiper is incremented to the desired position, the cs pin should be forced to v ih to ensure that unexpected transitions (on the sck pin do not cause the wiper setting to change). driving the cs pin to v ih should occur as soon as possible (within device specifications) after the last desired increment occurs. figure 7-7: continuous increment command - sdi and sdo states. a d 3 a d 2 a d 1 a d 0 0 1xxa d 3 a d 2 a d 1 a d 0 0 1xxa d 3 a d 2 a d 1 a d 0 01xx 1111111*11111111*11111111*1 note 1, 2 111111 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note 3, 4 11111111111111 0 0 0 0 0 0 0 0 0 0 note 3, 4 1111111111111111111111 0 0 note 3, 4 (incr command (n+1) ) (incr command (n+2) ) (incr command (n+3) ) sdi sdo command byte command byte command byte note 1: only functions when writing the volatile wiper registers (ad3:ad0) 0h and 1h. 2: valid address/command combination. 3: invalid address/command combination. 4: if an error condition occurs (cmderr = l), a ll following sdo bits will be low until the cmderr condition is cleared (the cs pin is forced to the inactive state). downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 55 mcp414x/416x/424x/426x 7.8 decrement wiper normal and high voltage the decrement command is an 8-bit command. the decrement command can only be issued to volatile memory locations. the format of the command is shown in figure 7-6 . an decrement command to the volatile memory location changes that location after a properly formatted command (8-clocks) have been received. decrement commands provide a quick and easy method to modify the value of the volatile wiper location by -1 with minimal overhead. figure 7-8: decrement command - sdi and sdo states. 7.8.1 single decrement typically the cs pin starts at the inactive state (v ih ), but may be already be in the active state due to the completion of another command. figure 6-7 through figure 6-8 show possible waveforms for a single decrement. the decrement operation requires that the cs pin be in the active state (v il or v ihh ). typically the cs pin will be in the inactive state (v ih ) and is driven to the active state (v il or v ihh ). then the 8-bit decrement command (command byte) is clocked in on the sdi pin by the sck pins. the sdo pin drives the cmderr bit on the 7th clock. the wiper value will decrement from the wipers full scale value (100h on 8-bit devices and 80h on 7-bit devices). above the wipers full scale value (8-bit =101h to 1ffh, 7-bit = 81h to ffh), the decrement command is disabled. if the wiper register has a zero scale value (000h), then the wiper value will not decrement. see ta b l e 7 - 4 for additional information on the decrement command vs. the current volatile wiper value. the decrement commands only require the decrement command byte, while the cs pin is active (v il or v ihh ) for a single decrement. after the wiper is decremented to the desired position, the cs pin should be forced to v ih to ensure that unexpected transitions on the sck pin do not cause the wiper setting to change. driving the cs pin to v ih should occur as soon as possible (within device specifications) after the last desired decrement occurs. table 7-5: decrement operation vs. volatile wiper value note: table 7-2 shows the valid addresses for the decrement wiper command. other addresses are invalid. a d 3 a d 2 a d 1 a d 0 10xx 1111111*1 note 1, 2 111111 0 0 note 1, 3 (decr command (n+1)) sdi sdo command byte note 1: only functions when writing the volatile wiper registers (ad3:ad0) 0h and 1h. 2: valid address/command combination. 3: invalid address/command combination all following sdo bits will be low until the cmderr condition is cleared. (the cs pin is forced to the inactive state). 4: if a command error (cmderr) occurs at this bit location (*), then all following sdo bits will be driven low until the cs pin is driven inactive (v ih ). current wiper setting wiper (w) properties decrement command operates? 7-bit pot 8-bit pot 3ffh 081h 3ffh 101h reserved (full-scale (w = a)) no 080h 100h full-scale (w = a) yes 07fh 041h 0ffh 081 w = n 040h 080h w = n (mid-scale) yes 03fh 001h 07fh 001 w = n 000h 000h zero scale (w = b) no downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 56 ? 2008 microchip technology inc. 7.8.2 continuous decrements continuous decrements are possible only when writing to the volatile memory registers (address 00h, 01h, and 04h). figure 7-9 shows a continuous decrement sequence for three continuous writes . the writes do not need to be to the same volatile memory address. when executing an continuous decrement commands, the selected wiper will be altered from n to n-1 for each decrement command received. the wiper value will decrement from the wipers full scale value (100h on 8-bit devices and 80h on 7-bit devices). above the wipers full-scale value (8-bit =101h to 1ffh, 7-bit = 81h to ffh), the decrement command is disabled. if the wiper register has a zero scale value (000h), then the wiper value will not decrement. see table 7-4 for additional information on the decrement command vs. the current volatile wiper value. decrement commands can be sent repeatedly without raising cs until a desired condition is met. the value in the volatile wiper register can be read using a read command and written to the corresponding non-volatile wiper eeprom using a write command. when executing a continuous command string, the decrement command can be followed by any other valid command. the wiper terminal will move after the command has been received (8th clock). after the wiper is decremented to the desired position, the cs pin should be forced to v ih to ensure that unexpected transitions ( on the sck pin do not cause the wiper setting to change). driving the cs pin to v ih should occur as soon as possible (within device specifications) after the last desired decrement occurs. figure 7-9: continuous decrement command - sdi and sdo states. a d 3 a d 2 a d 1 a d 0 1 0xxa d 3 a d 2 a d 1 a d 0 1 0xxa d 3 a d 2 a d 1 a d 0 10xx 1111111*11111111*11111111*1 note 1, 2 111111 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note 3, 4 11111111111111 0 0 0 0 0 0 0 0 0 0 note 3, 4 1111111111111111111111 0 0 note 3, 4 (decr command (n-1) ) (decr command (n-1) ) (decr command (n-1) ) sdi sdo command byte command byte command byte note 1: only functions when writing the volatile wiper registers (ad3:ad0) 0h and 1h. 2: valid address/command combination. 3: invalid address/command combination. 4: if an error condition occurs (cmderr = l), all following sdo bits will be low until the cmderr condition is cleared (the cs pin is forced to the inactive state). downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 57 mcp414x/416x/424x/426x 7.9 modify write protect or wiperlock technology (high voltage) enable and disable this command is a special case of the high voltage decrement wiper and high voltage increment wiper commands to the non-volatile memory locations 02h, 03h, and 0fh. this command is used to enable or disable either the software write protect, wiper 0 wiperlock technology, or wiper 1 wiperlock technol- ogy. ta b l e 7 - 6 shows the memory addresses, the high voltage command and the result of those commands on the non-volatile wp, wl0, 0r wl1 bits. the format of the command is shown in figure 7-8 (enable) or figure 7-6 (disable). 7.9.1 single enable write protect or wiperlock technology (high voltage) figure 6-7 through figure 6-8 show possible waveforms for a single modify write protect or wiperlock technology command. a modify write protect or wiperlock technology command will only start an eeprom write cycle (t wc ) after a properly formatted command (8-clocks) has been received and the cs pin transitions to the inactive state (v ih ). after the cs pin is driven inactive (v ih ), the serial interface may immediately be re-enabled by driving the cs pin to the active state (v il or v ihh ). during an eeprom write cycl e, only serial commands to volatile memory (addresses 00h, 01h, 04h, and 05h) are accepted. all other serial commands are ignored until the eeprom write cycle (t wc ) completes. this allows the host controller to operate on the volatile wiper registers and the tcon register, and to read the status register. the eewa bit in the status register indicates the status of an eeprom write cycle. table 7-6: address map to modify write protect and wiperlock technology memory address commands and result high voltage decrement wiper high voltage increment wiper 00h wiper 0 register is decremented wiper 0 register is incremented 01h wiper 1 register is decremented wiper 1 register is incremented 02h wl0 is enabled wl0 is disabled 03h wl1 is enabled wl1 is disabled 04h (1) tcon register not changed, cmderr bit is set tcon register not changed, cmderr bit is set 05h - 0eh (1) reserved reserved 0fh wp is enabled wp is disabled note 1: reserved addresses: increment or decrement commands are invalid for these addresses. downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 58 ? 2008 microchip technology inc. notes: downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 59 mcp414x/416x/424x/426x 8.0 applications examples non-volatile digital potentiometers have a multitude of practical uses in modern electronic circuits. the most popular uses include precision calibration of set point thresholds, sensor trimming, lcd bias trimming, audio attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and offset trimming. the mcp414x/416x/424x/426x devices can be used to replace the common mechani- cal trim pot in applications where the operating and terminal voltages are within cmos process limitations (v dd = 2.7v to 5.5v). 8.1 split rail applications all inputs that would be used to interface to a host controller support high voltage on their input pin. this allows the mcp4xxx device to be used in split power rail applications. an example of this is a battery application where the pic ? mcu is directly powered by the battery supply (4.8v) and the mcp4xxx dev ice is powered by the 3.3v regulated voltage. for spi applications, these inputs are: cs sck sdi (or sdi/sdo) wp shdn figure 8-1 through figure 8-2 show three example split rail systems. in this syst em, the mcp4xxx interface input signals need to be able to support the pic mcu output high voltage (v oh ). in example #1 ( figure 8-1 ), the mcp4xxx interface input signals need to be able to support the pic mcu output high voltage (v oh ). if the split rail voltage delta becomes too large, then the customer may be required to do some level shif ting due to mcp4xxx v oh levels related to host controller v ih levels. in example #2 ( figure 8-2 ), the mcp4xxx interface input signals need to be able to support the lower voltage of the pic mcu output high voltage level (v oh ). table 8-1 shows an example pic microcontroller i/o voltage specifications and the mcp4xxx specifica- tions. so this pic mcu operating at 3.3v will drive a v oh at 2.64v, and for the mcp4xxx operating at 5.5v, the v ih is 2.47v. therefore, the interface signals meet specifications. figure 8-1: example split rail system 1. figure 8-2: example split rail system 2. table 8-1: v oh - v ih comparisons pic (1) mcp4xxx (2) comment v dd v ih v oh v dd v ih v oh 5.5 4.4 4.4 2.7 1.215 (3) 5.0 4.0 4.0 3.0 1.35 (3) 4.5 3.6 3.6 3.3 1.485 (3) 3.3 2.64 2.64 4.5 2.025 (3) 3.0 2.4 2.4 5.0 2.25 (3) 2.7 2.16 2.16 5.5 2.475 (3) note 1: v oh minimum = 0.8 * v dd ; v ol maximum = 0.6v v ih minimum = 0.8 * v dd ; v il maximum = 0.2 * v dd ; 2: v oh minimum (sda only) =; v ol maximum = 0.2 * v dd v ih minimum = 0.45 * v dd ; v il maximum = 0.2 * v dd 3: the only mcp4xxx output pin is sdo, which is open-drain (or open-drain with internal pull-up) with high voltage support voltage regulator 5v 3v pic mcu mcp4xxx sdics sckwp shdn sdi cs sck wp shdn sdo sdo voltage regulator 3v 5v pic mcu mcp4xxx sdics sckwp shdn sdi cs sck wp shdn sdo sdo downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 60 ? 2008 microchip technology inc. 8.2 techniques to force the cs pin to v ihh the circuit in figure 8-3 shows a method using the tc1240a doubling charge pump. when the shdn pin is high, the tc1240a is off, and the level on the cs pin is controlled by the pic? microcontrollers (mcus) io2 pin. when the shdn pin is low, the tc1240a is on and the v out voltage is 2 * v dd . the resistor r 1 allows the cs pin to go higher than the voltage such that the pic mcus io2 pin clamps at approximately v dd . figure 8-3: using the tc1240a to generate the v ihh voltage. the circuit in figure 8-4 shows the method used on the mcp402x non-volatile digital potentiometer evalua- tion board (part number: mcp402xev). this method requires that the system voltage be approximately 5v. this ensures that when the pic10f206 enters a brown-out condition, there is an insufficient voltage level on the cs pin to change the stored value of the wiper. the mcp402x non-volatile digital potentiome- ter evaluation board users guide (ds51546) contains a complete schematic. gp0 is a general purpose i/o pin, while gp2 can either be a general purpose i/o pin or it can output the internal clock. for the serial commands, configure the gp2 pin as an input (high impedance). the output state of the gp0 pin will determine the voltage on the cs pin (v il or v ih ). for high-voltage serial commands, force the gp0 output pin to output a high level (v oh ) and configure the gp2 pin to output the internal clock. this will form a charge pump and increase the voltage on the cs pin (when the system voltage is approximately 5v). figure 8-4: mcp4xxx non-volatile digital potentiometer evaluation board (mcp402xev) implementation to generate the v ihh voltage. 8.3 using shutdown modes figure 8-5 shows a possible application circuit where the independent terminals could be used. disconnecting the wiper allo ws the transistor input to be taken to the bias voltage level (disconnecting a and or b may be desired to reduce system current). disconnecting terminal a modifies the transistor input by the r bw rheostat value to the common b. disconnecting terminal b modifies the transistor input by the r aw rheostat value to the common a. the common a and common b connections could be connected to v dd and v ss . figure 8-5: example application circuit using terminal disconnects. cs pic mcu mcp402x r 1 io1 io2 c 2 tc1240a v in shdn c+ c- v out c 1 cs pic10f206 mcp4xxx r 1 gp0 gp2 c 2 c 1 balance bias w b input input to b a s e of transistor (or amplifier) a common b common a downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 61 mcp414x/416x/424x/426x 8.4 design considerations in the design of a system with the mcp4xxx devices, the following considerations should be taken into account: power supply considerations layout considerations 8.4.1 power supply considerations the typical application will require a bypass capacitor in order to filter high-fr equency noise, which can be induced onto the power supply's traces. the bypass capacitor helps to minimize the effect of these noise sources on signal integrity. figure 8-6 illustrates an appropriate bypass strategy. in this example, the recommended bypass capacitor value is 0.1 f. this capacitor should be placed as close (within 4 mm) to the device power pin (v dd ) as possible. the power source supplying these devices should be as clean as possible. if the application circuit has separate digital and analog power supplies, v dd and v ss should reside on the analog plane. figure 8-6: typical microcontroller connections. 8.4.2 layout considerations inductively-coupled ac transients and digital switching noise can degrade the input and output signal integrity, potentially masking the mcp4xxxs performance. careful board layout minimizes these effects and increases the signal-to-noise ratio (snr). multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving th e performance that the silicon is capable of providing. particularly harsh environ- ments may require shieldin g of critical signals. if low noise is desired, breadboards and wire-wrapped boards are not recommended. 8.4.3 resistor tempco characterization curves of the resistor temperature coefficient (tempco) are shown in figure 2-8 , figure 2-19 , figure 2-29 , and figure 2-39 . these curves show that the resistor network is designed to correct for the change in resistance as temperature increases. this technique reduces the end to end change is r ab resistance. 8.4.4 high voltage tolerant pins high voltage support (v ihh ) on the serial interface pins supports two features. these are: in-circuit accommodation of split rail applications and power supply sync issues user configuration of th e non-volatile eeprom, write protect, and wiperlock feature v dd v dd v ss v ss mcp414x/416x/ 424x/426x 0.1 f pic ? microcontroller 0.1 f u/d cs w b a note: in many applications, the high voltage will only be present at the manufacturing stage so as to lock the non-volatile wiper value (after calibration) and the contents of the eeprom. this ensures that the since high voltage is not present under normal operating conditions, that these values can not be modified. downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 62 ? 2008 microchip technology inc. notes: downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 63 mcp414x/416x/424x/426x 9.0 development support 9.1 development tools several development tools are available to assist in your design and evaluation of the mcp4xxx devices. the currently available tools are shown in ta b l e 9 - 1 . these boards may be purchased directly from the microchip web site at www.microchip.com. 9.2 technical documentation several additional technical documents are available to assist you in your design and development. these technical documents include application notes, technical briefs, and design guides. ta b l e 9 - 2 shows some of these documents. table 9-1: development tools table 9-2: technical documentation board name part # supported devices mcp42xx digital potentiometer pictail plus demo board mcp42xxdm-ptpls mcp42xx mcp4xxx digital potentiometer daughter board (1) mcp4xxxdm-db mcp42xxx, mcp42xx, mcp4021, and mcp4011 8-pin soic/msop/tssop/dip ev aluation board soic8ev any 8-pin device in dip, soic, msop, or tssop package 14-pin soic/msop/dip evaluation board soic14ev any 14-pin device in dip, soic, or msop package note 1: requires the use of a picdem demo board (see users guide for details) application note number title literature # an1080 understanding digital potentiome ters resistor variations ds01080 an737 using digital potentiometers to design low pass adjustable filters ds00737 an692 using a digital potentiometer to optimize a precision single supply photo detect ds00692 an691 optimizing the digital potentiometer in precision circuits ds00691 an219 comparing digital potentiometers to mechanical potentiometers ds00219 digital potentiometer design guide ds22017 signal chain design guide ds21825 downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 64 ? 2008 microchip technology inc. notes: downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 65 mcp414x/416x/424x/426x 10.0 packaging information 10.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 8-lead dfn (3x3) example : part number code part number code mcp4141-502e/mf daaj mcp4142-502e/mf dabc mcp4141-103e/mf daak mcp4142-103e/mf dabd mcp4141-104e/mf daam mcp4142-104e/mf dabf mcp4141-503e/mf daal mcp4142-503e/mf dabe mcp4161-502e/mf daat mcp4162-502e/mf dabg mcp4161-103e/mf daau mcp4162-103e/mf dabh mcp4161-104e/mf daaw mcp4162-104e/mf dabk mcp4161-503e/mf daav mcp4162-503e/mf dabj daaj e816 256 xxxxxyww nnn 8-lead msop xxxxxx ywwnnn example 414152 816256 part number code part number code mcp4141-502e/ms 414152 mcp4142-502e/ms 414252 mcp4141-103e/ms 414113 mcp4142-103e/ms 414213 mcp4141-104e/ms 414114 mcp4142-104e/ms 414214 mcp4141-503e/ms 414153 mcp4142-503e/ms 414253 mcp4161-502e/ms 416152 mcp4162-502e/ms 416252 mcp4161-103e/ms 416113 mcp4162-103e/ms 416213 mcp4161-104e/ms 416114 mcp4162-104e/ms 416214 mcp4161-503e/ms 416153 mcp4162-503e/ms 416253 downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 66 ? 2008 microchip technology inc. legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e xxxxxnnn 8-lead pdip xxxxxxxx yyww e/p 256 example 4141-502 0816 3 e 8-lead soic xxxxxxxx xxxxyyww nnn example 4141502e sn^^^0816 256 3 e downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 67 mcp414x/416x/424x/426x package marking information (continued) 10-lead dfn (3x3) example : part number code part number code mcp4242-502e/mf baem mcp4262-502e/mf baew mcp4242-103e/mf baep mcp4262-103e/mf baex mcp4242-104e/mf baer mcp4262-104e/mf baez mcp4242-503e/mf baeq mcp4262-503e/mf baey baeh 0816 256 xxxx yyww nnn 10-lead msop xxxxxx ywwnnn example 423252 816256 part number code part number code mcp4242-502e/ms 424252 mcp4262-502e/ms 426252 mcp4242-103e/ms 424213 mcp4262-103e/ms 426213 mcp4242-104e/ms 424214 mcp4262-104e/ms 426214 mcp4242-503e/ms 424253 mcp4262-503e/ms 426253 14-lead tssop xxxxxxxx yyww nnn example 4261502e 0816 256 14-lead pdip xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn example 14-lead soic (.150) xxxxxxxxxxx xxxxxxxxxxx yywwnnn example mcp4261 502e/sl^^ 0816256 3 e mcp4261 502e/p^^ 0816256 3 e xxxxx 16-lead qfn (4x4) xxxxxx yywwnnn example xxxxxx 4261 502 0816256 e/ml^^ 3 e downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 68 ? 2008 microchip technology inc.

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? 2008 microchip technology inc. ds22059b-page 83 mcp414x/416x/424x/426x appendix a: revision history revision b (december 2008) the following is the list of modifications: 1. updated i pu specifications to specify test conditions and new limit. 2. updated dfn and qfn package in package types (top view) , to include exposed thermal pad samples (ep). 3. added new descriptions in section 3.0 pin descriptions . 4. added new development tool support item. 5. updated package outline section. revision a (august 2007) original release of this document. appendix b: migrating from the mcp41xxx and mcp42xxx devices this is intended to give an overview of some of the differences to be aware of when migrating from the mcp41xxx and mcp42xxx devices. b.1 mcp41xxx to mcp41xx differences here are some of the differences to be aware of: 1. si pin is now sdi/sdo pin, and the contents of the device memory can be read 2. need to address the terminal connect feature (tcon register) of mcp41xx 3. mcp41xx supports software shutdown mode 4. new 5 k version 5. mcp41xx have 7-bit resolution options 6. mcp41xx are non-volatile 7. alternate pinout versions (for rheostat configuration) 8. verify devices electrical specifications 9. interface signals are now high voltage tolerant 10. interface signals now have internal pull-up resistors b.2 mcp42xxx to mcp42xx differences here are some of the differences to be aware of: 1. hardware reset (rs ) pin replace by hardware write protect (wp ) pin 2. daisy chaining of devices is no longer supported 3. sdo pin allows contents of device memory to be read 4. need to address the terminal connect feature (tcon register) of mcp42xx 5. mcp42xx supports software shutdown mode 6. new 5 k version 7. mcp42xx have 7-bit resolution options 8. mcp42xx are non-volatile 9. alternate package/pinout versions (for rheostat configuration) 10. verify devices electrical specifications 11. interface signals are now high voltage tolerant 12. interface signals now have internal pull-up resistors downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 84 ? 2008 microchip technology inc. notes: downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 85 mcp414x/416x/424x/426x product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . part no. x /xx -xxx resistance package temperature range device device mcp4141: single non-volatile 7-bit potentiometer mcp4141t: single non-volatile 7-bit potentiometer (tape and reel) mcp4142: single non-volatile 7-bit rheostat mcp4142t: single non-volatile 7-bit rheostat (tape and reel) mcp4161: single non-volatile 8-bit potentiometer mcp4161t: single non-volatile 8-bit potentiometer (tape and reel) mcp4162: single non-volatile 8-bit rheostat mcp4162t: single non-volatile 8-bit rheostat (tape and reel) mcp4241: dual non-volatile 7-bit potentiometer mcp4241t: dual non-volatile 7-bit potentiometer (tape and reel) mcp4242: dual non-volatile 7-bit rheostat mcp4242t: dual non-volatile 7-bit rheostat (tape and reel) mcp4261: dual non-volatile 8-bit potentiometer mcp4261t: dual non-volatile 8-bit potentiometer (tape and reel) mcp4262: dual non-volatile 8-bit rheostat mcp4262t: dual non-volatile 8-bit rheostat (tape and reel) resistance version: 502 = 5 k ? 103 = 10 k ? 503 = 50 k ? 104 = 100 k ? temperature range i = -40 c to +85 c (industrial) e= - 4 0 c to +125 c (extended) package mf = plastic dual flat no-lead (3x3 dfn), 8/10-lead ml = plastic quad flat no-lead (4x4 qfn), 16-lead ms = plastic micro small outline (msop), 8-lead p = plastic dual in-line (pdip) (300 mil), 8/14-lead sn = plastic small outline (soic), (150 mil), 8-lead sl = plastic small outline (soic), (150 mil), 14-lead st = plastic thin shrink small outline (tssop), 14-lead un = plastic micro small outline (msop), 10-lead examples: a) mcp4141-502e/xx: 5 k ? , 8ld device b) mcp4141t-502e/xx: t/r, 5 k ? , 8ld device c) mcp4141-103e/xx: 10 k ? , 8-ld device d) mcp4141t-103e/xx: t/r, 10 k ? , 8ld device e) mcp4141-503e/xx: 50 k ? , 8ld device f) mcp4141t-503e/xx: t/r, 50 k ? , 8ld device g) mcp4141-104e/xx: 100 k ? , 8ld device h) mcp4141t-104e/xx: t/r, 100 k ? , 8ld device a) mcp4142-502e/xx: 5 k ? , 8ld device b) mcp4142t-502e/xx: t/r, 5 k ? , 8ld device c) mcp4142-103e/xx: 10 k ? , 8-ld device d) mcp4142t-103e/xx: t/r, 10 k ? , 8ld device e) mcp4142-503e/xx: 50 k ? , 8ld device f) mcp4142t-503e/xx: t/r, 50 k ? , 8ld device g) mcp4142-104e/xx: 100 k ? , 8ld device h) mcp4142t-104e/xx: t/r, 100 k ? , 8ld device a) mcp4161-502e/xx: 5 k ? , 8ld device b) mcp4161t-502e/xx: t/r, 5 k ? , 8ld device c) mcp4161-103e/xx: 10 k ? , 8-ld device d) mcp4161t-103e/xx: t/r, 10 k ? , 8ld device e) mcp4161-503e/xx: 50 k ? , 8ld device f) mcp4161t-503e/xx: t/r, 50 k ? , 8ld device g) mcp4161-104e/xx: 100 k ? , 8ld device h) mcp4161t-104e/xx: t/r, 100 k ? , 8ld device a) mcp4162-502e/xx: 5 k ? , 8ld device b) mcp4162t-502e/xx: t/r, 5 k ? , 8ld device c) mcp4162-103e/xx: 10 k ? , 8-ld device d) mcp4162t-103e/xx: t/r, 10 k ? , 8ld device e) mcp4162-503e/xx: 50 k ? , 8ld device f) mcp4162t-503e/xx: t/r, 50 k ? , 8ld device g) mcp4162-104e/xx: 100 k ? , 8ld device h) mcp4162t-104e/xx: t/r, 100 k ? , 8ld device a) mcp4241-502e/xx: 5 k ? , 8ld device b) mcp4241t-502e/xx: t/r, 5 k ? , 8ld device c) mcp4241-103e/xx: 10 k ? , 8-ld device d) mcp4241t-103e/xx: t/r, 10 k ? , 8ld device e) mcp4241-503e/xx: 50 k ? , 8ld device f) mcp4241t-503e/xx: t/r, 50 k ? , 8ld device g) mcp4241-104e/xx: 100 k ? , 8ld device h) mcp4241t-104e/xx: t/r, 100 k ? , 8ld device a) mcp4242-502e/xx: 5 k ? , 8ld device b) mcp4242t-502e/xx: t/r, 5 k ? , 8ld device c) mcp4242-103e/xx: 10 k ? , 8-ld device d) mcp4242t-103e/xx: t/r, 10 k ? , 8ld device e) mcp4242-503e/xx: 50 k ? , 8ld device f) mcp4242t-503e/xx: t/r, 50 k ? , 8ld device g) mcp4242-104e/xx: 100 k ? , 8ld device h) mcp4242t-104e/xx: t/r, 100 k ? , 8ld device a) mcp4261-502e/xx: 5 k ? , 8ld device b) mcp4261t-502e/xx: t/r, 5 k ? , 8ld device c) mcp4261-103e/xx: 10 k ? , 8-ld device d) mcp4261t-103e/xx: t/r, 10 k ? , 8ld device e) mcp4261-503e/xx: 50 k ? , 8ld device f) mcp4261t-503e/xx: t/r, 50 k ? , 8ld device g) mcp4261-104e/xx: 100 k ? , 8ld device h) mcp4261t-104e/xx: t/r, 100 k ? , 8ld device a) mcp4262-502e/xx: 5 k ? , 8ld device b) mcp4262t-502e/xx: t/r, 5 k ? , 8ld device c) mcp4262-103e/xx: 10 k ? , 8-ld device d) mcp4262t-103e/xx: t/r, 10 k ? , 8ld device e) mcp4262-503e/xx: 50 k ? , 8ld device f) mcp4262t-503e/xx: t/r, 50 k ? , 8ld device g) mcp4262-104e/xx: 100 k ? , 8ld device h) mcp4262t-104e/xx: t/r, 100 k ? , 8ld device xx = mf for 8/10-lead 3x3 dfn = ml for 16-lead qfn = ms for 8-lead msop = p for 8/14-lead pdip = sn for 8-lead soic = sl for 14-lead soic = st for 14-lead tssop = un for 10-lead msop version downloaded from: http:///
mcp414x/416x/424x/426x ds22059b-page 86 ? 2008 microchip technology inc. notes: downloaded from: http:///
? 2008 microchip technology inc. ds22059b-page 87 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, rfpic, smartshunt and uni/o are registered trademarks of microchip te chnology incorporated in the u.s.a. and other countries. filterlab, linear active thermistor, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered tradema rks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, application maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, pickit, picdem, picdem.net, pictail, pic 32 logo, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, total endurance, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2008, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchips c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. downloaded from: http:///
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